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exar corporation 48720 kato road, fremont ca, 94538 ? (510) 668-7000 ? fax (510) 668-7017 ? www.exar.com xrt73lc00a e3/ds3/sts-1 line interface unit may 2011 rev. 1.0.2 general description the xrt73lc00a ds3/e3/sts-1 line interface unit is a low power cmos version of the xrt73l00a and consists of a line transmitter and receiver integrated on a single chip and is designed for ds3, e3 or sonet sts-1 applications. xrt73lc00a can be configured to support the e3 (34.368 mbps), ds3 (44.736 mbps) or the sonet sts-1 (51.84 mbps) rates. in the transmit direction, the xrt73lc00a encodes input data to either b3zs (for ds3/sts-1 applications) or hdb3 (for e3 applications) format and converts the data into the appropriate pulse shapes for transmission over coaxial cable via a 1:1 transformer. in the receive direction the xrt73lc00a performs equalization on incoming signals, performs clock recovery, decodes data from either b3zs or hdb3 format, converts the rece ive data into ttl/cmos format, checks for los or lol conditions and detects and declares the occurrence of line code violations. the xrt73lc00a also contains a 4-wire microprocessor serial interface for accessing the on- chip command registers. features ? incorporates an improved timing recovery circuit and is pin and functional compatible to xrt73l00a ? meets e3/ds3/sts-1 jitter tolerance requirements ? full loop-back capability ? transmit and receive power down modes ? full redundancy support ? contains a 4-wire microprocessor serial interface ? uses minimum external components ? low power cmos design ? single +3.3v power supply ? 5 v tolerant pins ? -40c to +85c operating temperature range ? available in a 44 pin tqfp package applications ? interfaces to e3, ds3 or sonet sts-1 networks ? csu/dsu equipment ? pcm test equipment ? fiber optic terminals ? multiplexers
xrt73lc00a 2 e3/ds3/sts-1 line interface unit rev. 1.0.2 ordering information f igure 1. b lock d iagram of the xrt73lc00a p art n umber p ackage t ype o perating t emperature r ange xrt73lc00aiv 44 pin tqfp (10mm x 10mm) -40c to +85c agc/ equalizer serial processor interface peak detector los detector slicer clock recovery data recovery invert loop mux hdb3/ b3zs decoder losthr sdi sdo/(lcv) sclk cs regreset rtip rring reqdis device monitor mtip mring dmo transmit logic duty cycle adjust ttip tring pulse shaping hdb3/ b3zs encoder e3 sts-1/ds3 host/(hw) rlol exclk ict rclkinv tx control dr/sr rlos llb rlb endecdis taos tpdata tndata tclk txlev txoff rclk1 rneg rpos lcv/(rclk2)
xrt73lc00a 3 rev. 1.0.2 e3/ds3/sts-1 line interface unit f igure 2. p in o ut of the xrt73lc00a in the 44 p in tqfp lcv/(rclk2) 44 43 42 41 40 39 38 37 36 35 34 12 13 14 15 16 17 18 19 20 21 22 23 24 33 32 31 30 29 28 27 26 25 xrt73lc00a (top view) txlev taos txavdd dmo txagnd rtip agnd rxagnd rring rxavdd regreset/ rclk2inv reqdis losthr llb rlb sts1/ds3 e3 host/hw sdi/(losmuten) sdo/(lcv) sclk/(endecdis) cs/(dr/sr) rpos rneg rclk1 rxdvdd dvdd rxdgnd exclk dgnd rlos rlol mtip mring txavdd ttip tring txagnd tndata tpdata tclk txoff ict 11 10 1 2 3 4 5 6 7 8 9
xrt73lc00a i e3/ds3/sts-1 line interface unit rev. 1.0.2 table of contents features ....................................................................................................................... ...........................1 applications ........... ................ ................ ................ ................. ................ ............. .......... ........................1 f igure 1. b lock d iagram of the xrt73lc00a .................................................................................................................... ...... 2 ordering information....... ................ ................ ................. .............. .............. ...........2 f igure 2. p in o ut of the xrt73lc00a in the 44 p in tqfp ...................................................................................................... 3 pin description.............. ................ ................ ................. ................ ................. .............4 electrical characteristics ........ ................ ................ ............... .............. ...........12 absolute maximum ratings ....................................................................................................... ..12 dc e lectrical c haracteristics ..............................................................................................................12 ac e lectrical c haracteristics ..............................................................................................................13 f igure 3. t iming d iagram of the t ransmit t erminal i nput i nterface .................................................................................... 14 f igure 4. t iming d iagram of the r eceive t erminal o utput i nterface .................................................................................. 14 f igure 5. t ransmit p ulse a mplitude t est c ircuit for ds3, e3 and sts-1 r ates ................................................................ 14 ac electrical characte ristics (cont?d) l ine s ide p arameters .............................................17 f igure 6. itu-t g.703 t ransmit o utput p ulse t emplate for e3 a pplications ..................................................................... 18 f igure 7. b ellcore gr-499-core t ransmit o utput p ulse t emplate for ds3 a pplications ............................................. 18 f igure 8. b ellcore gr-253-core t ransmit o utput p ulse t emplate for sonet sts-1 a pplications ............................ 19 f igure 9. m icroprocessor s erial i nterface d ata s tructure .............................................................................................. 19 ac electrical characteristics (cont.) .....................................................................................20 f igure 10. t iming d iagram for the m icroprocessor s erial i nterface ................................................................................ 20 system description ......... ................. ................ ................ ............... .............. ...........21 t he t ransmit s ection ............................................................................................................................... 21 t he r eceive s ection ............................................................................................................................... ..21 t he m icroprocessor s erial i nterface ..................................................................................................21 t able 1: r ole of m icroprocessor s erial i nterface pins when the xrt73lc00a is operating in the h ardware m ode .. 22 1.0 selecting the data rate ................................................................................................. ...........23 t able 2: s electing the d ata r ate for the xrt73lc00a via the e3 and sts-1/ds3 input pins (h ardware m ode ) ........... 23 c ommand r egister cr4 (a ddress = 0 x 04) .............................................................................................23 t able 3: s electing the d ata r ate for the xrt73lc00a v ia the sts-1/ds3 and the e3 b it - fields w ithin c ommand r egister cr4 (host m ode ) .............................................................................................................................. ......................... 24 2.0 the transmit section .................................................................................................... ..............24 2.1 the transmit logic block ........... .............. .............. .............. ........... ............ ........... ......... .................... 24 f igure 11. t he t ypical i nterface for the t ransmission of d ata in a d ual -r ail f ormat f rom the t ransmitting t erminal e quipment to the t ransmit s ection of the xrt73lc00a ....................................................................................... 25 f igure 12. h ow the xrt73lc00a s amples the d ata on the tpdata and tndata i nput p ins .......................................... 25 2.1.1 accepting single-rail data from the terminal equipment ............................................................... 2 5 c ommand r egister cr1 (a ddress = 0 x 01) .............................................................................................26 f igure 13. t he b ehavior of the tpdata and tclk i nput s ignals w hile the t ransmit l ogic b lock is a ccepting s ingle -r ail d ata f rom the t erminal e quipment .......................................................................................................................... 26 2.2 the transmit clock duty cycle adjust circuitry .............. .............. ........... ........... ........... ....... 26 2.3 the hdb3/b3zs encoder block ............................................................................................. ............... 26 2.3.1 b3zs encoding .......................................................................................................... ............................................. 26 f igure 14. a n e xample of b3zs e ncoding ............................................................................................................................... 27 2.3.2 hdb3 encoding.......................................................................................................... ............................................. 27 f igure 15. a n e xample of hdb3 e ncoding .............................................................................................................................. 2 7 2.3.3 enabling/disabling the hdb3/b3zs encoder ............................................................................... .............. 27 c ommand r egister cr2 (a ddress = 0 x 02) .............................................................................................28 2.4 the transmit pulse shaper ci rcuitry ....... .............. .............. .............. .............. ........... ........... ....... 28 2.4.1 enabling the transmit line build-out circuit ........................................................................... .............. 28 c ommand r egister cr1 (a ddress = 0 x 01) .............................................................................................28 2.4.2 disabling the transmit line build-out circuit .......................................................................... .............. 29 c ommand r egister cr1 (a ddress = 0 x 01) .............................................................................................29 2.4.3 design guideline for setting the transmit line build-out circuit ................................................ 29 2.4.4 the transmit line build-out circuit and e3 applications................................................................ ... 29 2.5 interfacing the transmit section of the xrt 73lc00a to the line ...... .............. ........... ....... 29 f igure 16. r ecommended s chematic for i nterfacing the t ransmit s ection of the xrt73lc00a to the l ine ................. 30 t ransformer r ecommendations ................................................................................................... 30 3.0 the receive section ..................................................................................................... ................32
xrt73lc00a ii rev. 1.0.2 e3/ds3/sts-1 line interface unit 3.1 interfacing the receive sect ion of the xrt73lc00a to the line ......................................... 32 f igure 17. r ecommended s chematic for i nterfacing the r eceive s ection of the xrt73lc00a to the l ine (t ransformer - c oupling ).............................................................................................................................. ....................................... 32 f igure 18. r ecommended s chematic for i nterfacing the r eceive s ection of the xrt73lc00a to the l ine (c apacitive -c ou - pling ).............................................................................................................................. .............................................. 33 3.2 the receive equalizer block ............................................................................................. ................ 33 3.2.1 guidelines for setting the receive equalizer ........................................................................... ............ 33 f igure 19. t he t ypical a pplication for the s ystem i nstaller ............................................................................................. 34 c ommand r egister cr2 (a ddress = 0 x 02)............................................................................................. 35 3.3 peak detector and slicer ................................................................................................ ................... 35 3.4 clock recovery pll ...................................................................................................... ......................... 35 3.5 the hdb3/b3zs decoder ................................................................................................... ...................... 36 3.5.1 b3zs decoding ds3/sts-1 applications ................................................................................... ..................... 36 f igure 20. a n e xample of b3zs d ecoding ............................................................................................................................... 36 3.5.2 hdb3 decoding e3 applications.......................................................................................... ............................ 36 f igure 21. a n e xample of hdb3 d ecoding .............................................................................................................................. 3 7 3.5.3 enabling/disabling the hdb3/b3zs decoder ............................................................................... .............. 37 c ommand r egister cr2 (a ddress = 0 x 02)............................................................................................. 37 3.6 los declaration/clearance . .............. .............. .............. .............. .............. .............. .......... ............... 37 3.6.1 the los declaration/clearance criteria for e3 applications....................................................... 38 f igure 22. t he s ignal l evels that the xrt73lc00a d eclares and c lears los (e3 m ode o nly )..................................... 38 f igure 23. t he b ehavior of the los o utput i ndicator i n r esponse to the l oss of s ignal and the r estoration of s ignal 39 3.6.2 the los declaration/clearance criteria for ds3 and sts-1 applications ................................ 39 t able 4: t he alos (a nalog los) d eclare and c lear t hresholds for a given setting of losthr and reqen for ds3 and sts-1 a pplications ............................................................................................................................... ...................... 39 c ommand r egister cr0 (a ddress = 0 x 00)............................................................................................. 40 c ommand r egister cr2 (a ddress = 0 x 02)............................................................................................. 40 c ommand r egister cr0 (a ddress = 0 x 00)............................................................................................. 40 c ommand r egister cr2 (a ddress = 0 x 02)............................................................................................. 41 3.6.3 muting the recovered data while the los is being declared......................................................... 41 c ommand r egister cr3 (a ddress = 0 x 03)............................................................................................. 41 3.7 routing the recovered timing and data in formation to the rece iving terminal equip - ment .......................................................................................................................... .................................... 41 f igure 24. t he t ypical i nterface for the t ransmission of d ata in a d ual -r ail f ormat f rom the r eceive s ection of the xrt73lc00a to the r eceiving t erminal e quipment ................................................................................................ 42 f igure 25. h ow the xrt73lc00a o utputs d ata on the rpos and rneg o utput p ins .................................................... 42 f igure 26. t he b ehavior of the rpos, rneg and rclk1 s ignals w hen rclk1 is i nverted ............................................ 43 c ommand r egister cr3 (a ddress = 0 x 03)............................................................................................. 43 3.7.1 routing single-rail format data (binary data stream) to the receive terminal equipment 43 c ommand r egister cr3 (a ddress = 0 x 03)............................................................................................. 43 f igure 27. t he t ypical i nterface for the t ransmission of d ata in a s ingle -r ail f ormat f rom the r eceive s ection of the xrt73lc00a to the r eceiving t erminal e quipment ................................................................................................ 44 f igure 28. t he b ehavior of the rpos and rclk1 o utput s ignals w hile the xrt73lc00a is t ransmitting s ingle -r ail d ata to the r eceiving t erminal e quipment ....................................................................................................................... 44 4.0 diagnostic features of the xrt73lc00a ............................................................................. 44 4.1 the analog local loop-back mo de ............. .............. .............. .............. ........... ............ ........... ........ 44 f igure 29. t he a nalog l ocal l oop -b ack in the xrt73lc00a ............................................................................................... 45 c ommand r egister cr4 (a ddress = 0 x 04)............................................................................................. 45 4.2 the digital local loop-back mode ........... .............. .............. .............. .............. ............ ......... .......... 45 f igure 30. t he d igital l ocal l oop -b ack path in the xrt73lc00a ....................................................................................... 46 c ommand r egister cr4 (a ddress = 0 x 04)............................................................................................. 46 4.3 the remote loop-back mode ............................................................................................... ............... 46 f igure 31. t he r emote l oop -b ack p ath in the xrt73lc00a................................................................................................. 47 c ommand r egister cr4 (a ddress = 0 x 04)............................................................................................. 47 4.4 txoff features .......................................................................................................... .............................. 47 c ommand r egister cr1 (a ddress = 0 x 01)............................................................................................. 48 4.5 the transmit drive monitor fe atures ............. .............. .............. ........... ........... ............ .......... ...... 48 f igure 32. t he xrt73lc00a e mploying the t ransmit d rive m onitor f eatures ................................................................. 48 f igure 33. t wo liu? s , e ach m onitoring the t ransmit o utput s ignal of the o ther liu ic ............................................... 49 4.6 the taos (transmit all ones) feature .................................................................................... ....... 49 c ommand r egister cr1 (a ddress = 0 x 01)............................................................................................. 50
xrt73lc00a iii e3/ds3/sts-1 line interface unit rev. 1.0.2 5.0 the microprocessor serial interface ...............................................................................51 5.1 description of the command re gisters ........ .............. .............. .............. ............ ........... ........... .... 51 t able 5: a ddresses and b it f ormats of xrt73lc00a c ommand r egisters ......................................................................... 51 d escription of b it -f ields for e ach c ommand register .......................................................................51 5.1.1 command register - cr0 ................................................................................................. ................................... 51 5.1.2 command register - cr1 ................................................................................................. ................................... 52 5.1.3 command register - cr2 ................................................................................................. ................................... 54 5.1.4 command register - cr3 ................................................................................................. ................................... 54 5.1.5 command register - cr4 ................................................................................................. ................................... 55 t able 6: l oop -b ack m odes ............................................................................................................................... ......................... 55 5.2 operating the microprocessor serial interface. .............. .............. .............. ............... ......... 55 f igure 34. m icroprocessor s erial i nterface d ata s tructure ............................................................................................ 56 ordering information....... ................ ................ .............. ............... .............. ...........58 package dimensions........ ................. ................ ................ ............... .............. ...........58 r evision h istory ............................................................................................................................... ........59
xrt73lc00a 4 rev. 1.0.2 e3/ds3/sts-1 line interface unit pin description pin description p in # s ymbol t ype d escription 1 txlev i transmit line build-out enable/disable select: this input pin is used to enable or disable the transmit line build-out circuit in the xrt73lc00a. setting this pin to ?high? disables the li ne build-out circuit. in this mode, the xrt73lc00a outputs partially shaped pulses onto the line via the ttip and tring output pins. setting this pin to ?low? enables the line build-out circuit. in this mode, the xrt73lc00a outputs partially-shaped pu lses onto the line via the ttip and tring output pins. to comply with the isolated dsx-3/stsx -1 pulse template requirements per bellcore gr-499-core or bellcore gr-253-core: 1. set this input pin to a "1" if the cable length between the cross-connect and the transmit output of the xrt73lc00a is greater than 225 feet. 2. set this input pin to a "0" if the cable length between the cross-connect and the transmit output of the xrt73lc00a is less than 225 feet. this pin is active only if both of the following are true: (a) the xrt73lc00a is configured to operate in either the ds3 or sonet sts-1 modes and (b) the xrt73lc00a is configured to operate in the hardware mode. n ote : this pin should be tied to gnd if the xrt73lc00a is to be operated in the host mode. 2 taos i transmit all ones select: a ?high? on this pin causes a continuous ami all ?1?s? pattern to be transmitted onto the line. the frequency of this ?1?s? pattern is determined by tclk. n otes : 1. this input pin is ignored if the xrt73lc00a is operating in the host mode. 2. tie this pin to gnd if the xrt73lc00a is going to be operating in the host mode. 3 txavdd **** transmit analog power supply 4 dmo o drive monitor output: if no bipolar line signal is detected on t he ttip/tring output pins via the mtip and mring input pins for 12832 tclk periods, then the dmo output pin tog - gles and remains ?high? until the next bipolar pulse is detected. 5 txagnd **** transmit analog ground 6 agnd **** analog ground (substrate) 7 rxagnd **** receive analog ground 8 rtip i receive tip input: this input pin along with rring is used to receive the line signal from the remote ds3/e3/sts-1 terminal. 9 rring i receive ring input: this input pin along with rtip is used to receive the line signal from the remote ds3/e3/sts-1 terminal. 10 rxavdd **** receive analog power supply
xrt73lc00a 5 e3/ds3/sts-1 line interface unit rev. 1.0.2 11 regreset / (rclk2inv) i register reset input pin (inv ert rclk2 output - select): the function of this pin depends upon whether the xrt73lc00a is operating in the host mode or in the hardware mode. host mode - register reset input pin: setting this input pin ?low? causes the xrt73lc00a to reset the contents of the command registers to their default settin gs and operating conf iguration. this pin is internally pulled ?high?. hardware mode - invert rclk2 output select: setting this input pin ?low? configures the receive section of the xrt73lc00a to output the recovered data via the rp os and rneg output pins on the rising edge of the rclk2 output signal. setting this input pin ?high? configures the receive section to output the recov - ered data on the falling edge of the rclk2 output signal. 12 reqdis i receive equalization disable input: setting this input pin ?high? disables the internal receive equalizer in the xrt73lc00a. setting this pin ?low? enables the internal receive equalizer. the guidelines for enabling and disabling the receive equalizer are described in section 3.2 . n otes : 1. this input pin is ignored if the xrt73lc00a is operating in the host mode. 2. tie this pin to gnd if the xrt73lc00a is going to be operating in the host mode. 13 losthr i loss of signal threshold control: this input pin is used to select the los (loss of signal) declaration and clear - ance thresholds for the analog los detector circuit. two settings are provided by forcing this signal to either gnd or vdd. n ote : this pin is only applicable during ds3 or sts-1 operations. 14 llb i local loop-back select: this input pin along with rlb dictates which loop-back mode the xrt73lc00a is operating in. a ?high? on this pin with rlb being set to ?low? configures the xrt73lc00a to operate in the analog local loop-back mode. a ?high? on this pin with rlb also being set to ?high? configures the xrt73lc00a to operate in the digital local loop-back mode. n otes : 1. this input pin is ignored if the xrt73lc00a is operating in the host mode. 2. tie this pin to gnd if the xrt73lc00a is going to be operating in the host mode. pin description p in #s ymbol t ype d escription
xrt73lc00a 6 rev. 1.0.2 e3/ds3/sts-1 line interface unit 15 rlb i remote loop-back select: this input pin along with llb dictat es which loop-back mode the xrt73lc00a is operating in. a ?high? on this pin with llb being set to ?low? configures the xrt73lc00a to operate in the remote loop-back mode. a ?high? on this pin with llb also being set to ?high? configures the xrt73lc00a to operate in the digital local loop-back mode. n otes : 1. this input pin is ignored if the xrt73lc00a is operating in the host mode. 2. tie this pin to gnd if the xrt73lc00a is going to be operating in the host mode. 16 sts-1/ ds3 i sts-1/ ds3 select input: a ?high? on this pin configures the clock recovery phase locked loop to set its vco center frequency to around 51.84 mhz for sonet sts-1 operations. a ?low? on this pin configures the clock recovery phase locked loop to set its vco center frequency to around 44.736 mhz for ds3 operations. n otes : 1. the xrt73lc00a ignores this pin if the e3 pin (pin 17) is set to ?1?. 2. this input pin is ignored if the xrt73lc00a is operating in the host mode. 3. tie this pin to gnd if the xrt73lc00a is going to be operating in the host mode. 17 e3 i e3 select input: a ?high? on this pin configures the xrt73lc00a to operate in the e3 mode. a ?low? on this pin configures the xrt7 3lc00a to check the state of the sts-1/ ds3 input pin. n otes : 1. this input pin is ignored if the xrt73lc00a is operating in the host mode. 2. tie this pin to gnd if the xrt73lc00a is going to be operating in the host mode. 18 host/ hw i host/ hw mode select: this input pin is used to enable or disable the microprocessor serial interface (e.g., consisting of the sdi, sdo, sclk, cs and regreset pins). setting this input pin ?high? enables the microprocessor serial interface (e.g. configures the xrt73lc00a to operate in the host mode). in this mode, the xrt73lc00a is configured by writing data into the on-chip command registers via the microprocessor serial interface. when the xrt73lc00a is operating in the host mode, it ignores the states of many of the discrete input pins. setting this input pin ?low? disables th e microprocessor serial interface (e.g., configures the xrt73lc00a to operate in the hardware mode). in this mode, many of the external input control pins are functional. pin description p in #s ymbol t ype d escription
xrt73lc00a 7 e3/ds3/sts-1 line interface unit rev. 1.0.2 19 sdi/ (losmuten) i serial data input for th e microprocessor serial in terface (host mode) or mute-upon-los enable input (hardware mode): the function of this input pin depends upon whether the xrt73lc00a is operat - ing in the host or the hardware mode. serial data input for the microprocessor serial interface (host mode): this pin is used to read or write data in to the command registers of the micro - processor serial interface. the read/w rite bit, the addres s values of the com - mand registers and data value to be written during write operations are applied to this pin. this input is sampled on the rising edge of the sclk pin (pin 21). mute-upon-los enable input (hardware mode): in the hardware mode this input pin is used to configure the xrt73lc00a to mute the recovered data via the rpos and rneg output pins whenever it declares an los condition. setting this input pin ?high? configures the xrt73lc00a to automatically pull the rpos and rneg output pins to gnd whenever it is declaring an los condi - tion, thereby muting the data being out put to the terminal equipment. setting this input pin ?low? configures the xrt73lc00a to not automatically mute the recovered data whenever an los condition is declared. 20 sdo/(lcv) o serial data output from the controller port/(line code violation output (lcv) indicator.): the function of this input pin depends upon whether the xrt73lc00a is operat - ing in the host or the hardware mode. host mode - microprocessor serial interface - serial data output. this pin serially outputs the contents of the specified command register during read operations. the data on this pin is updated on the falling edge of the sclk input signal. this pin is tri-stated upon completion of data transfer. hardware mode - line code violation output indicator. this pin pulses ?high? for one bit period any time the receive section of the xrt73lc00a detects a line code violati on in the incoming e3, ds3 or sts-1 data stream. 21 sclk/ (endecdis) i microprocessor serial interface clock signal/encoder disable: host mode - microprocessor serial interface clock signal this signal is used to sample the data on the sdi pin on the rising edge of this signal. during read operations, the micr oprocessor serial interface updates the sdo output on the falling edge of this signal. hardware mode - b3zs/hdb3 encoder/decoder disable setting this input pin ?high? disa bles both the b3zs/hdb3 encoder and decoder. this setting configures the transmit section of the xrt73lc00a to transmit data to the remote terminal equipment via the ami line code. this set - ting also configures the receive section to receive a line signal via the ami line code. setting this input pin ?low? enables both the b3zs/hdb3 encoder and decoder. this setting configures the transmit se ction of the xrt73lc00a to transmit data in the b3zs format for ds3/sts-1 applications or the hdb3 format for e3 applications. this setting configures the receive section to receive a line signal that has been encoded into the b3zs or hdb3 line code. pin description p in #s ymbol t ype d escription
xrt73lc00a 8 rev. 1.0.2 e3/ds3/sts-1 line interface unit 22 cs /(dr/ sr ) i microprocessor serial interface - chip select/encoder and decoder disable the function of this input pin depends upon whether the xrt73lc00a is operat - ing in the host or the hardware mode. host mode - chip select input: the local microprocessor must assert this pin (e.g., set it to ?0?) in order to enable communication with the xrt73lc 00a via the microprocessor serial interface. hardware mode - dual-rail/single-rail select input: setting this input pin ?high? configures the xrt73lc00a to operate in the dual- rail mode. when the xrt73lc00a is ope rating in this mode, then the receive section of the liu ic outputs the recovered data via both rpos and rneg output pins. setting this input pin ?low? configures the xrt73lc00axrt73lc00a to oper - ate in the single-rail mode. when the xrt73lc00a is operating in this mode, the receive section of the liu ic outp uts the recovered data via the rpos output pin in a binary data stream. no dat a will output via the rneg output pin. 23 rlol o receive loss of lock output indicator this output pin toggles ?h igh? if the xrt73lc00a has detected a loss of lock condition. the xrt73lc00a declares an lol (loss of lock) condition if the recovered clock frequency deviates from the reference clock frequency (avail - able at the exclk input pin) by more than 0.5%. n ote : the rclk1/2 output pins are sourced by the signal applied at the exclk input pin anytime the xrt73lc00a declares an lol condition. 24 rlos o receive loss of signal output indicator this output pin toggles ?high? if the xr t73lc00a has detected a loss of signal condition in the incoming line signal. the criteria the xrt73lc00a uses to declare an los condition depends upon whether the device is operating in the e3 or ds3/sts-1 mode. 25 dgnd **** digital ground 26 dvdd **** digital power supply 27 exclk i external reference clock input: apply a line-rate clock signal to this input pin. this signal is a 34.368mhz clock signal for e3 applications, a 44.736 mhz clock signal for ds3 applications or a 51.84 mhz clock signal for sonet sts-1 applications. n ote : this input pin functions as the sour ce of the rxclk output clock signal any time the xrt73lc00a declares an lol condition. 28 rxdgnd **** receiver digital ground 29 rxdvdd **** receiver digital power supply pin description p in #s ymbol t ype d escription
xrt73lc00a 9 e3/ds3/sts-1 line interface unit rev. 1.0.2 30 lcv/(rclk2) o line code violation indicator/receive clock output pin 2: the function of this pin depends upon wh ether the xrt73lc00a is operating in the host mode, the hardware mode or user selection. host mode - line code violation indicator output: if the xrt73lc00a is configured to operate in the host mode, then this pin functions as the lcv output pin by defaul t. however, by using the on-chip com - mand registers, this pin can be configur ed to function as the second receive clock signal output pin rclk2. hardware mode - receive clock output pin 2: this output pin is the recovered clock signal from the incoming line signal. the receive section of the xrt73lc00a out puts data via the rpos and rneg out - put pins on the rising edge of this clock signal. n ote : if the xrt73lc00a is operating in the host mode and this pin is configured to function as the additional receive clock signal output pin, then the xrt73lc00a can be configured to update the data on the rpos and rneg output pins on the falling edge of this clock signal. 31 rclk1 o receive clock output pin 1: this output pin is the recovered clock signal from the incoming line signal. the receive section of the xrt73lc00a out puts data via the rpos and rneg out - put pins on the rising edge of this clock signal. n ote : if the xrt73lc00a is operating in the host mode, the device can be configured to update the data on the rpos and rneg output pins on the falling edge of this clock signal. 32 rneg o receive negative pulse output: this output pin pulses ?high? whenever the xrt73lc00a has received a nega - tive polarity pulse in the incoming line signal at the rtip/rring inputs. n otes : 1. if the b3zs/hdb3 decoder is enabled, the zero suppression patterns in the incoming line signal (such as: "00v", "000v", "b0v", "b00v") are not reflected at this output. 2. this output pin is inactive if the xrt73lc00a has been configured to operate in the single-rail mode. 33 rpos o receive positive pulse output: this output pin pulses ?high? whenever the xrt73lc00a has received a posi - tive polarity pulse in the incoming line signal at the rtip/rring inputs. n ote : if the b3zs/hdb3 decoder is enabled, the zero suppression patterns in the incoming line signal (such as: "0 0v", "000v", "b0v", "b00v") are not reflected at this output. 34 ict i in-circuit test input: setting this input pin ?low? causes all digital and analog outputs to go into a high-impedance state in order to permit in-circuit testing. set this pin ?high? for normal operation. n ote : this pin is internally pulled ?high?. pin description p in #s ymbol t ype d escription
xrt73lc00a 10 rev. 1.0.2 e3/ds3/sts-1 line interface unit 35 txoff i transmitter off input: setting this input pin ?high? configures the xrt73lc00a to turn off the transmit - ter in the device. when the transmitter is shut-off, the ttip and tring output pins will be tri-stated in the xrt73lc00a. n otes : 1. this input pin is not ignored if the xrt73lc00a is operating in the host mode. 2. tie this pin to gnd if the xrt73lc00a is going to be operating in the host mode. 36 tclk i transmit clock input for tpdata and tndata: this input pin must be driven at 34.368 mhz for e3 applications, 44.736mhz for ds3 applications, or 51.84mhz for sonet sts-1 applications. the xrt73lc00a uses this signal to sample the tpdata and tndata input pins. the xrt73lc00a is configured to sample these two pins on the falling edge of this signal. if the xrt73lc00a is operating in the host mode, then the device can be con - figured to sample the tpdata and tndata input pins on the rising edge of tclk. 37 tpdata i transmit positive data input: the xrt73lc00a samples this pin on the falling edge of tclk. if the device samples a ?1? at this input pin, then it generates and transmits a positive polarity pulse to the line. n otes : 1. the data should be applied to this input pin if the transmit section is configured to accept single-rail data from the terminal equipment. 2. if the xrt73lc00a is operating in the host mode, then the xrt73lc00a can be configured to sample the tpdata pin on either the rising or falling edge of tclk. 38 tndata i transmit negative data input: the xrt73lc00a samples this pin on the falling edge of tclk. if the device samples a ?1? at this input pin, then it generates and transmits a negative polarity pulse to the line. n otes : 1. this input pin is ignored and should be tied to gnd if the transmit section is configured to accept single-rail data from the terminal equipment. 2. if the xrt73lc00a is operating in the host mode, then the xrt73lc00a can be configured to sample the tndata pin on either the rising or falling edge of tclk. 39 txagnd - transmit analog ground 40 tring o transmit tring output: the xrt73lc00a uses this pin along with ttip to transmit a bipolar line signal via a 1:1 transformer. n ote : this output pin along with ttip is tri-stated anytime the txoff input pin or bit-field is set ?high?. pin description p in #s ymbol t ype d escription
xrt73lc00a 11 e3/ds3/sts-1 line interface unit rev. 1.0.2 41 ttip o transmit tip output: the xrt73lc00a uses this pin along with tring to transmit a bipolar line sig - nal via a 1:1 transformer. n ote : this output pin along with tring is tri-stated anytime the txoff input pin or bit-field is set ?high?. 42 txavdd - transmit analog power supply 43 mring i monitor ring input: this input pin along with the mtip pin func tion as the input pins for the transmit drive monitor. these two input pins are used to determine whether or not a bipolar line signal is being output via the ttip and tring output pins. the transmit drive monitor circuit will toggle the dmo output pin ?high? denoting a transmit line fault condition if no bi polar pulses are detected via the ttip/ tring output pins for 128 bit-periods. connect this input pin to the tring output pin via a 270 ohm resistor. n ote : tie this input pin to gnd if you do not intend to use the transmit drive monitor. 44 mtip i monitor tip input: this input pin along with the mring pin function as the input pins for the trans - mit drive monitor. these two input pins are to be used to determine whether or not a bipolar line signal is being output via the ttip and tring output pins. the transmit drive monitor circuit will toggle the dmo output pin ?high? denoting a transmit line fault condition if no bi polar pulses are detected via the ttip/ tring output pins for 128 bit periods. connect this input pin to the ttip output pin via a 270 ohm resistor. n ote : tie this input pin to gnd if you do not intend to use the transmit drive monitor. pin description p in #s ymbol t ype d escription
xrt73lc00a 12 rev. 1.0.2 e3/ds3/sts-1 line interface unit electrical characteristics * not applicable to pins with pull-up/pull-down resistors. absolute maximum ratings p ower s upply -0.5 to +3.465v s torage t emperature -65 c to 150 c i nput v oltage at a ny p in -0.5v to 5.0v p ower d issipation tqfp p ackage 1.2w i nput c urrent at a ny p in +100 m a esd r ating (m il -s td -883, m-3015) 1500v dc electrical characteristics (ta = 25 c, vdd = 3.3v + 5%, unless otherwise specified) s ymbol p arameter m in . t yp . m ax . u nits v ddd dc supply voltage 3.135 3.3 3.465 v v dda dc supply voltage 3.135 3.3 3.465 v i cc supply current (measured while transmitting and receiving all ?1?s?) 125 ma v il input low voltage 0.8 v v ih input high voltage 2.0 5.0 v v ol output low voltage, iout = -4.0ma 0.4 v v oh output high voltage, iout = 4.0ma 2.8 v i l input leakage current* 10 ? a
xrt73lc00a 13 e3/ds3/sts-1 line interface unit rev. 1.0.2 ac electrical characteristics (ta = 25 c, vdd = 3.3v + 5%, unless otherwise specified) s ymbol p arameter m in . t yp . m ax . u nits terminal side timing parameters (see figure 3 & figure 4) tclk clock duty cycle (ds3/sts-1) 30 50 70 % tclk clock duty cycle (e3) 30 50 70 % tclk frequency (sonet sts-1) 51.84 mhz tclk frequency (ds3) 44.736 mhz tclk frequency (e3) 34.368 mhz t rtx tclk clock rise time (10% to 90%) 4 ns t ftx tclk clock fall time (90% to 10%) 4 ns t tsu tpdata/tndata to tclk falling set up time 3 ns t tho tpdata/tndata to tclk falling hold time 3 ns t lcvo rclk to rising edge of lcv output delay 2.5 ns t tdy ttip/tring to tclk rising propagation delay time 0.6 14 ns rclk clock duty cycle 45 50 55 % rclk frequency (sonet sts-1) 51.84 mhz rclk frequency (ds3) 44.736 mhz rclk frequency (e3) 34.368 mhz t co rclk to rpos/rneg delay time 4 ns t rrx rclk clock rise time (10% to 90%) 2 4 ns t frx rclk clock fall time (10% to 90%) 1.5 3 ns c i input capacitance 10 pf c l load capacitance 10 pf
xrt73lc00a 14 rev. 1.0.2 e3/ds3/sts-1 line interface unit f igure 3. t iming d iagram of the t ransmit t erminal i nput i nterface f igure 4. t iming d iagram of the r eceive t erminal o utput i nterface f igure 5. t ransmit p ulse a mplitude t est c ircuit for ds3, e3 and sts-1 r ates tpdata or tndata ttip or tring tclk t tsu t tho t rtx t ftx t tdy rclk t rrx t frx rpos or rneg lcv t lcvo t co r1 31.6 ? r2 31.6 ? ttip tring 1:1 r3 75 ? t1
xrt73lc00a 15 e3/ds3/sts-1 line interface unit rev. 1.0.2 ac electrical characteristics (c ont?d) line side parameters (ta = 25 c, vdd = 3.3v + 5%, unless otherwise specified) s ymbol p arameter m in . t yp . m ax . u nits e3 application parameters transmit line characteristics (see figure 5) transmit output pulse amplit ude (measured at secondary out - put of transformer) 0.9 1.0 1.1 vpk transmit output pulse amplitude ratio 0.95 1.00 1.05 transmit output pulse width 12.5 14.55 16.5 ns transmit output pulse width ratio 0.95 1.00 1.05 transmit output jitter with jitter-free input clock at tclk 0.02 0.05 uipp receive line characteristics receive sensitivity (length of cable) 1200 1400 feet interference margin -20 -17 db signal level to declare loss of signal -35 db signal level to clear loss of signal -15 db occurrence of los to los declaration time 10 100 255 ui termination of los to los clearance time 10 100 255 ui intrinsic jitter (all "1?s" pattern) 0.01 ui jitter tolerance @ jitter frequency = 100hz 64 ui jitter tolerance @ jitter frequency = 1khz 30 ui jitter tolerance @ jitter frequency = 10khz 4 ui jitter tolerance @ jitter frequency = 800khz 0.15 0.20 ui
xrt73lc00a 16 rev. 1.0.2 e3/ds3/sts-1 line interface unit ac electrical characteristics (c ont?d) line side parameters (ta = 25 c, vdd = 3.3v + 5%, unless otherwise specified) s ymbol p arameter m in . t yp . m ax . u nits sonet sts-1 application parameters transmit line characteristics (see figure 5) transmit output pulse amp litude (measured with txlev = 0) 0.65 0.75 0.90 vpk transmit output pulse amp litude (measured with txlev = 1) 0.93 0.98 1.08 vpk transmit output pulse width 8.6 9.65 10.6 ns transmit output pulse amplitude ratio 0.9 1.0 1.1 transmit output jitter with jitter-free clock input at tclk 0.02 0.05 uipp receive line characteristics receive sensitivity (length of cable) 900 1100 feet signal level to declare or clear loss of signal (see table 4) mv intrinsic jitter (all "1?s" pattern) 0.03 ui jitter tolerance @ jitter frequency = 100hz 64 ui jitter tolerance @ jitter frequency = 1khz 64 ui jitter tolerance @ jitter frequency = 10khz 5 ui jitter tolerance @ jitter frequency = 400khz 0.15 0.35 ui
xrt73lc00a 17 e3/ds3/sts-1 line interface unit rev. 1.0.2 ac electrical characteristics (cont?d) line side parameters (ta = 25 c, vdd = 3.3v + 5%, unless otherwise specified) s ymbol p arameter m in . t yp . m ax . u nits ds3 application parameters transmit line characteristics (see figure 5) transmit output pulse amplitude (measured at 0 feet, txlev = 0) 0.65 0.75 0.85 vpk transmit output pulse amplitude (measured at 0 feet, txlev = 1) 0.9 1.0 1.1 vpk transmit output pulse width 10.10 11.18 12.28 ns transmit output pulse amplitude ratio 0.9 1.0 1.1 transmit output jitter with jitter-free input clock at tclk 0.02 0.05 uipp receive line characteristics receive sensitivity (length of cable) 900 1100 feet signal level to declare or clear loss of signal (see table 4) mv intrinsic jitter (all one?s pattern) 0.01 ui jitter tolerance @ jitter frequency = 100hz 64 ui jitter tolerance @ jitter frequency = 1khz 64 ui jitter tolerance @ jitter frequency = 10khz 5 ui jitter tolerance @ jitter freq uency = 300khz -- (cat ii) 0.35 0.45 ui
xrt73lc00a 18 rev. 1.0.2 e3/ds3/sts-1 line interface unit figure 6, figure 7 and figure 8 present the pulse template requirements for the e3, ds3 and sts-1 rates. f igure 6. itu-t g.703 t ransmit o utput p ulse t emplate for e3 a pplications f igure 7. b ellcore gr-499-core t ransmit o utput p ulse t emplate for ds3 a pplications 0% 50% v = 100% 14.55ns nominal pulse 12.1ns (14.55 - 2.45) 17 ns (14.55 + 2.45) 8.65 ns 10% 10% 20% ds3 pulse template -0.2 0 0.2 0.4 0.6 0.8 1 1.2 - 1 - 0 .9 -0.8 -0. 7 - 0 .6 -0.5 -0. 4 -0 .3 -0.2 -0. 1 0 0 . 1 0.2 0 .3 0 . 4 0.5 0 .6 0 . 7 0.8 0 .9 1 1.1 1.2 1 . 3 1.4 time, in ui normalized amplitude lower curve upper curve
xrt73lc00a 19 e3/ds3/sts-1 line interface unit rev. 1.0.2 n otes : 1. a4 and a5 are always "0". 2. r/w = "1" for "read" operations 3. r/w = "0" for "write" operations a shaded pulse, denotes a ?don?t care? value. f igure 8. b ellcore gr-253-core t ransmit o utput p ulse t emplate for sonet sts-1 a pplications f igure 9. m icroprocessor s erial i nterface d ata s tructure sts-1 pulse template -0.2 0 0.2 0.4 0.6 0.8 1 1.2 -1 -0.9 -0.8 -0.7 -0.6 - 0 .5 - 0 .4 -0 .3 -0. 2 -0.1 0 0. 1 0. 2 0. 3 0. 4 0. 5 0 . 6 0 . 7 0.8 0. 9 1 1. 1 1 . 2 1 . 3 1 . 4 time, in ui normalized amplitude lower curve upper curve d0 d1 d2 0 0 0 d4 d3 high z sdo a0 d0 r/w d1 a6 0 0 a3 a2 a1 d7 d6 d5 d4 d3 d2 sdi 12345678910111213141516 sclk cs high z
xrt73lc00a 20 rev. 1.0.2 e3/ds3/sts-1 line interface unit ac electrical characteristics (cont.) (ta = 25 c, vdd = 3.3v + 5%, unless otherwise specified) s ymbol p arameter m in . t yp . m ax . u nits microprocessor serial inte rface timing (see figure 10) t 21 cs low to rising edge of sclk setup time 5 ns t 22 sclk falling edge to cs low assertion time 20 ns t 23 sdi to rising edge of sclk setup time 50 ns t 24 sdi to rising edge of sclk hold time 50 ns t 25 sclk ?low? time 240 ns t 26 sclk ?high? time 240 ns t 27 sclk period 500 ns t 28 cs low to rising edge of sclk hold time 5 ns t 29 cs inactive time 250 ns t 30 falling edge of sclk to sdo valid time 200 ns t 31 falling edge of sclk to sdo invalid time 100 ns t 32 falling edge of sclk or rising edge of cs to high z 100 ns t 33 rise/fall time of sdo output 40 ns f igure 10. t iming d iagram for the m icroprocessor s erial i nterface sdi r/w a1 a0 cs sclk cs sclk sdi sdo d0 d1 d2 d7 t22 t21 t23 t24 t25 t26 t27 t28 t29 t30 t31 t32 t33 hi-z hi-z
xrt73lc00a 21 e3/ds3/sts-1 line interface unit rev. 1.0.2 system description a functional block diagram of the xr t73lc00a e3/ds3/sts-1 transceiver ic (see figure 1) shows that the device contains three distinct sections: ? the transmit section ? the receive section ? the microprocessor serial interface the transmit section the transmit section accepts ttl/cmos level signals from the terminal equipment in either a single-rail or dual-rail format. the transmit section then takes this data and does the following: ? encodes the data into the b3zs format if the ds3 or sonet sts-1 modes have been selected or into the hdb3 format if the e3 mode has been selected. ? converts the cmos level b3zs or hdb3 encoded data in to pulses with shapes that are compliant with the various industry standard pulse template requirements. ? drives these pulses onto the line via the ttip and tring output pins across a 1:1 transformer. n ote : the transmit section drives a "1" (or a mark) on the line by driving either a positive or negative polarity pulse across the 1:1 transformer within a given bit period. the transmit section drives a "0" (or a sp ace) onto the line by driving no pulse onto the line. the receive section the receive section receives a bipolar signal from the line either via a 1:1 transformer or a 0.01mf capacitor. as the receive section receives this line signal it does the following: ? adjusts the signal level through an agc circuit. ? optionally equalizes this signal for cable loss. ? attempts to quantify a bit-interval within the line signal as either a ?1?, ?-1? or a ?0? by slicing this data. this sliced data is used by the clock recovery pll to recover the timing element within the line signal. ? the sliced data is routed to the hdb3/b3zs decoder, during which the original data content as transmitted by the remote terminal equipment is restored to its original content. ? outputs the recovered clock and data to the local termi nal equipment in the form of cmos level signals via the rpos, rneg, rclk1 and rclk2 output pins. the microprocessor serial interface the xrt73lc00a can be configured to operate in either the hardware mode or the host mode. the hardware mode connect the host/ hw input pin (pin 18) to gnd to configure the xrt73lc00a to operate in the hardware mode. when the xrt73lc00a is operating in th e hardware mode, the following is true: 1. the microprocessor serial interface block is disabled. 2. the xrt73lc00a is configured via input pin settings. each of the pins associated with the microprocessor seri al interface takes on their alternative role as defined in ta b l e 1 .
xrt73lc00a 22 rev. 1.0.2 e3/ds3/sts-1 line interface unit 3. all of the remaining input pins become active. t able 1: r ole of m icroprocessor s erial i nterface pins when the xrt73lc00a is operating in the h ardware m ode p in # p in n ame f unction while in the h ardware m ode 11 regreset /(rclk2inv) rclk2inv 19 sdi/(losmuten) losmuten 20 sdo/(lcv) lcv 21 sclk/(endecdis) endecdis 22 cs /(dr/ sr ) dr/ sr 30 lcv/(rclk2) rclk2
xrt73lc00a 23 e3/ds3/sts-1 line interface unit rev. 1.0.2 the host mode to configure the xrt73lc00a to operat e in the host mode, connect the host/ hw input pin (pin 18) to vdd. when the xrt73lc00a is operating in the host mode, the following is true: 1. the microprocessor serial interface block is enabled. many configuration selecti ons are made by writing the appropriate data into the on-chip command registers via the microprocessor serial interface. 2. all of the following input pins are disabled: n pin 1 - txlev n pin 2 - taos n pin 12 - reqdis n pin 14 - llb n pin 15 - rlb n pin 16 - sts-1/ ds3 n pin 17 - e3 n pin 35 - txoff tie each of these pins to gnd if the xrt73lc0 0a ic is to be operated in the host mode. please see section 5.0 for a detailed description on o perating the microprocessor serial interface or the on- chip command registers. 1.0 selecting the data rate the xrt73lc00a can be configured to support the e3 (34.368 mbps), ds3 (44.736 mbps) or the sonet sts-1 (51.84 mbps) rates. selection of the data rate is dependent on whether the xrt73lc00a is operating in the hardware or host mode. a. when operating in the hardware mode. to configure the xrt73lc00a for the desired data rate, the e3 and the sts-1/ ds3 pins must be set to the appropriate logic states shown in ta b l e 2 . b. when operating in the host mode. to configure the xrt73lc00a for the desired data rate, appropriate values need to be written into the sts-1/ ds3 and e3 bit-fields in command register cr4. ta b l e 3 relates the values of these two bit-fields with respect to the selected data rates. t able 2: s electing the d ata r ate for the xrt73lc00a via the e3 and sts-1/ ds3 input pins (h ardware m ode ) d ata r ate s tate of e3 p in (p in 17) s tate of sts-1/ ds3 pin (p in 16) m ode of b3zs/hdb3 e ncoder / d ecoder b locks e3 (34.368 mbps) vdd x (don?t care) hdb3 ds3 (44.736 mbps) 0 0 b3zs sts-1 (51.84 mbps) 0 vdd b3zs command register cr4 (address = 0x04) d4 d3 d2 d1 d0 x sts-1/ ds3 e3 llb rlb x x x x x
xrt73lc00a 24 rev. 1.0.2 e3/ds3/sts-1 line interface unit the results of making these selections are: 1. the vco center frequency of the clock recovery phase-locked-loop is configured to match the selected data rate. 2. the b3zs/hdb3 encoder and decoder blocks are config ured to support b3zs en coding/decoding if the ds3 or sts-1 data rates were selected or, 3. the b3zs/hdb3 encoder and decoder blocks are conf igured to support hdb3 encoding/decoding if the e3 data rate was selected. 4. the on-chip pulse-shaping circuitry is configured to ge nerate transmit output pulses of the correct shape and width to meet the applicable pulse template requirement. 5. the los declaration/clearanc e criteria is established. 2.0 the transmit section figure 1 indicates that the transmit section of the xrt73lc00a consists of the following blocks: ? transmit logic block ? duty cycle adjust block ? hdb3/b3zs encoder ? pulse shaping block the purpose of the transmit section in the xrt73lc00a is to take ttl/cmos leve l data from the terminal equipment and encode it into a format that can: 1. be efficiently transmitted over coaxial cable at e3, ds3 or sts-1 data rates. 2. be reliably received by the remote terminal at the other end of the e3, ds3 or sts-1 data link. 3. comply with the applicable pulse template requirements. 2.1 the transmit logic block the purpose of the transmit logic block is to accept eith er dual-rail or single-rail (a binary data stream) ttl/ cmos level data and timing information from the terminal equipment. accepting dual-rail data from the terminal equipment the xrt73lc00a accepts dual-rail data from the terminal equipment via the following input signals: ? tpdata ? tndata ? tclk t able 3: s electing the d ata r ate for the xrt73lc00a v ia the sts-1/ ds3 and the e3 b it - fields w ithin c ommand r egister cr4 (host m ode ) s elected d ata r ate sts-1/ds3 e3 e3 don't care 1 ds3 0 0 sts-1 1 0
xrt73lc00a 25 e3/ds3/sts-1 line interface unit rev. 1.0.2 figure 11 illustrates the typical interface for the transmission of data in a dual-rail format between the terminal equipment and the transm it section of the xrt73lc00a. the manner that the liu handles dual-rail data is de scribed below and illu strated in figure 12. the xrt73lc00a typically samples the data on the tpdata and tndata input pins on the falling edge of tclk. tclk is typically a clock signal that is of the selected data rate frequency. for the e3 data rate, tclk is 34.368 mhz. for the ds3 data rate, tclk is 44.736 mhz and for the sonet sts-1 rate, tclk is 51.84 mhz. in general, if the xrt73lc00a samples a ?1? on the tpda ta input pin, the transmit section of the device ultimately generates a positive polarity pulse via the tt ip and tring output pins across a 1:1 transformer. if the xrt73lc00a samples a ?1? on the tndata input pin, the transmit section of the device ultimately generates a negative polarity pulse via the ttip and tring output pins across a 1:1 transformer. 2.1.1 accepting single-rail data from the terminal equipment do the following if data is to be transmited from the terminal equipment to the xrt73lc00a in single-rail format (a binary data stream) without havi ng to convert it into a dual-rail format. a. configure the xrt73lc00a to operate in the host mode or, f igure 11. t he t ypical i nterface for the t ransmission of d ata in a d ual -r ail f ormat f rom the t rans - mitting t erminal e quipment to the t ransmit s ection of the xrt73lc00a f igure 12. h ow the xrt73lc00a s amples the d ata on the tpdata and tndata i nput p ins exar e3/ds3/sts-1 liu terminal equipment (e3/ds3 or sts-1 framer) terminal equipment (e3/ds3 or sts-1 framer) txpos txneg txlineclk transmit logic block transmit logic block tpdata tndata tclk tclk tpdata tndata data 1 1 0 0
xrt73lc00a 26 rev. 1.0.2 e3/ds3/sts-1 line interface unit b. access the microprocessor serial interface and write a ?1? into the txbin (transmit binary) bit-field in command register 1. after taking these steps, the transm it logic block accepts single-rail data via the tpdata input pin. the xrt73lc00a samples this input pin on the falling edge of the tclk cl ock signal and enco des it into the appropriate bipolar line signal across the ttip and tring output pins. n otes : 1. in this mode the transmit logic block ignores the tndata input pin. 2. if the transmit section of the xrt 73lc00a is configured to accept single-ra il data from the terminal equipment, the b3zs/hdb3 encoder must be enabled. figure 13 illustrates the behavior of the tpdata and tclk signals when the transmit logic block has been configured to accept single-rail data from the terminal equipment. 2.2 the transmit clock duty cycle adjust circuitry the on-chip pulse-shaping circuitry in the transmit section of the xr t73lc00a has the responsibility for generating pulses of the shape and width to comply with the applicable pulse template requirement. the widths of these output pulses are de fined by the width of the half-per iod pulses in the tclk signal. allowing the widths of the pulses in th e tclk clock signal to vary significan tly could jeopardize the chip?s ability to generate transmit output pulses of the appropriate width, thereby fa iling the applicable pulse template requirement specification. the chips ability to generate compliant puls es could depend upon the duty cycle of the clock signal applied to the tclk input pin. in order to combat this phenomenon, the transmit clo ck duty cycle adjust circ uit was designed into the xrt73lc00a. the transmit clock duty cycle adjust cir cuitry is a pll that was designed to accept clock pulses via the tclk input pin at duty cycles ranging fr om 30% to 70% and to regen erate these signals with a 50% duty cycle. the xrt73lc00a transmit clock duty cycle adjust circuit alleviates the need to supply a signal with a 50% duty cycle to the tclk input pin. 2.3 the hdb3/b3zs encoder block the purpose of the hdb3/b3zs encoder block is to aid in the clock recovery process at the remote terminal equipment by ensuring an upper limit on the number of consecutive zeros that c an exist in the line signal. 2.3.1 b3zs encoding if the xrt73lc00a is configured to operate in th e ds3 or sonet sts-1 modes, then the hdb3/b3zs encoder block operates in the b3zs mode. when the encoder is operating in this mode, it parses through and command register cr1 (address = 0x01) d4 d3 d2 d1 d0 txoff taos txclkinv txlev txbin x x x x 1 f igure 13. t he b ehavior of the tpdata and tclk i nput s ignals w hile the t ransmit l ogic b lock is a ccepting s ingle -r ail d ata f rom the t erminal e quipment tclk tpdata data 1 1 0 0
xrt73lc00a 27 e3/ds3/sts-1 line interface unit rev. 1.0.2 searches the transmit binary data stream from the transmit logic block for the occurrence of three (3) consecutive zeros (?000?). if the b3zs encoder finds an occurrence of three consecutive zeros, it substitutes these three ?0?s? with either a "00v" or a "b0v" pattern. ?b? represents a bipolar pulse that is compliant with the alternating polarity requirements of the ami (alternate mark inversion) line code and ?v? represents a bipola r violation (e.g., a bipolar pulse that violates the alternating polarity requirements of the ami line code). the b3zs encoder decides whether to substitute with eit her a "00v" or a "b0v" pattern to insure that an odd number of bipolar pulses exist betwee n any two consecutive violation pulses. figure 14 illustrates the b3zs encoder at work with two separate strings of three (or more) co nsecutive zeros. 2.3.2 hdb3 encoding if the xrt73lc00a is configured to operate in the e3 mode, then the hdb3/b3zs en coder block operates in the hdb3 mode. when the encoder is operating in this mode, it parses through and searches the transmit data stream from the transmit logic block for the occu rrence of four (4) consecutive zeros (?0000?). if the hdb3 encoder finds an occurrence of four consecutive zeros, then it substitutes these four ?0?s? with either a ?000v? or a ?b00v? pattern to insure that an odd numb er of bipolar pulses exist between any two consecutive violation pulses. figure 15 illustrates the hdb3 enco der at work with two sepa rate strings of four (o r more) consecutive zeros. 2.3.3 enabling/disabling the hdb3/b3zs encoder the xrt73lc00a allows two methods to enable or disable the hdb3/b3zs encoder. if the xrt73lc00a is operat ing in the hardware mode. to enable the hdb3/b3zs encoder, set the endecdis inpu t pin (pin 21) to ?0?. to disable the hdb3/b3zs encoder, set the endecdis input pin (pin 21) to ?1?. f igure 14. a n e xample of b3zs e ncoding f igure 15. a n e xample of hdb3 e ncoding tclk tpos sr data encoded pdata encoded ndata 100 1 01 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 001 1 0 1 0 1 1 1 0 001 1 00 01 0100 0 0 0 00 0 0 0 1 111 1 000000000 0 1 0 0 0 0 01 01 01 01 01 01 01 01 1 10 10 1 0 10 1 0 1 line signal bv 0 v 0 0 0 tclk tpos sr data encoded pdata encoded ndata 100 1 01 00 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 001 1 0 1 0 1 1 1 0 001 1 00 01 0100 0 0 0 00 0 0 0 1 11 11 000000000 0 1 0 0 0 0 01 01 01 01 01 01 01 01 1 10 10 1 0 10 1 0 1 line signal bv 0 v 0 0 0 0
xrt73lc00a 28 rev. 1.0.2 e3/ds3/sts-1 line interface unit if the xrt73lc00a is oper ating in the host mode. to enable the hdb3/b3zs encoder, set the endecdi s bit-field in command register (cr2) to ?0?. to disable the hdb3/b3zs encoder, set the endecd is bit-field in command register (cr2) to ?1?. if either of these two methods is employed to disable the hdb3/b3zs encoder, the liu transmits the data onto the line as it is received via the tpdata and tndata input pins. 2.4 the transmit puls e shaper circuitry the transmit pulse shaper circuitry consists of a tr ansmit line build-out circuit which can be enabled or disabled by setting the txlev input pin or bit-field to ?h igh? or ?low?. the purpose of the transmit line build- out circuit is to permit configuring of the xrt73lc00a to transmit an output pulse which is compliant to either of the following bellcore pulse template requirements when measured at the digital cross connect system. each of these bellcore specifications further state that the cable length between the transmit output and the digital cross connect system can range anywhere from 0 to 450 feet. the isolated dsx-3 pulse templa te requirement per be llcore gr-499-core is illustrated in figure 7. the isolated stsx-1 pulse templa te requirement per bellcore gr-2 53-core is illustrated in figure 8. 2.4.1 enabling the transmit line build-out circuit if the transmit line build-o ut circuit is enabled, the xrt73lc00a outputs shaped pulses onto the line via the ttip and tring output pins. do the following to enable th e transmit line build-out circuit in the xrt73lc00a: ? if the xrt73lc00a is operating in the hardware mode, set thetxlev input pin (pin 1) to ?low? ? if the xrt73lc00a is operating in the host mode, set the txlev bit- field to ?0? as illustrated below. command register cr2 (address = 0x02) d4 d3 d2 d1 d0 reserved endecdis alosdis dlosdis reqdis x 0 x x x command register cr1 (address = 0x01) d4 d3 d2 d1 d0 txoff taos txclkinv txlev txbin 0 x x 0 x
xrt73lc00a 29 e3/ds3/sts-1 line interface unit rev. 1.0.2 2.4.2 disabling the transmit line build-out circuit if the transmit line build-out circuit is disabled, then the xrt73lc00a outputs partially-shaped pulses onto the line via the ttip and tring output pins. disable the transmit line build-out circuit in the xrt73lc00a by doing the following: ? if the xrt73lc00a is operating in the hardware mo de, set the txlev input pin (pin 1) to ?high? ? if the xrt73lc00a is operating in the host mode, set the txlev bit- field to ?1? as illustrated below. 2.4.3 design guideline for setting th e transmit line build-out circuit the setting oftxlev input pin or bit-field should be based upon the overall cable length between the transmitting terminal and the digital cross connect system where the pulse template measurements are made. if the cable length between the transmit ting terminal and the dsx-3 or stsx-1 is less than 225 feet, it is advisable to enable the transmit line build-out circui t by setting the txlev input pin or bit-field to "0". n ote : in this case the xrt73lc00a outputs shaped (e.g., not square-wave) pulses onto the line via the ttip and tring output pins. the shape of this output pulse is such that it complies wit h the pulse template requirements even when subjected to cable loss ranging from 0 to 225 feet. if the cable length between the transmitting ? terminal and the dsx-3 or stsx-1 is greater than 225 f eet, it is advisable to disable the transmit line build- out circuit by setting the txlev input pin or bit-field to "1". n ote : in this case the xrt73lc00a outputs partially-shaped pu lses onto the line via the ttip and tring output pins. the cable loss that these pulses experience over long cable lengths (e.g., greater than 225 feet) causes these pulses to be properly shaped and comply with the appropriate pulse template requirement. 2.4.4 the transmit line build-o ut circuit and e3 applications the itu-t g.703 pulse template requirements for e3 states that the e3 transmit output pulse should be measured at the secondary side of the transmit output transformer for pulse template compliance. there is no digital cross connect system pulse template requirement for e3 and the transmit line build-out circuit in the xrt73lc00a is disabled whenever it is operating in the e3 mode. 2.5 interfacing the transmit section of the xrt73lc00a to the line the e3, ds3 and sonet sts-1 specification documents all state that line signals transmitted over coaxial cable are to be terminated with 75 ohms. therefore, in terface the transmit section of the xrt73lc00a, as illustrated in figure 16 which shows two 31.6 ohm resistors in series with the primary side of the transformer. these two 31.6ohm resistors closely match the 75ohm lo ad termination resistor thereby minimizing transmit return loss. command register cr1 (address = 0x01) d4 d3 d2 d1 d0 txoff taos txclkinv txlev txbin 0 x x 1 x
xrt73lc00a 30 rev. 1.0.2 e3/ds3/sts-1 line interface unit transformer vendor information pulse corporate office 12220 world trade drive san diego, ca 92128 tel: (858)-674-8100 fax: (858)-674-8262 europe 1 & 2 huxley road f igure 16. r ecommended s chematic for i nterfacing the t ransmit s ection of the xrt73lc00a to the l ine transformer recommendations p arameter v alue turns ratio 1:1 primary inductance 40 ? h isolation voltage 1500vrms leakage inductance 0.6 ? h p art n umber v endor i nsulation p ackage t ype pe-68629 pulse 3000v large thru-hole pe-65966 pulse 1500v small thru-hole pe-65967 pulse 1500v small smt t3001 pulse 1500v small smt tg01-0406ns halo 1500v small smt tti 7601-sm trans-power 1500v small smt r1 31.6 ? r2 31.6 ? ttip tring 1:1 bnc t1
xrt73lc00a 31 e3/ds3/sts-1 line interface unit rev. 1.0.2 the surrey research park guildford, surrey gu2 5re united kingdom tel: 44-1483-401700 fax: 44-1483-401701 asia 150 kampong ampat #07-01/02 ka centre singapore 368324 tel: 65-287-8998 fax: 65-280-0080 website: http://www.pulseeng.com halo electronics corporate office p.o. box 5826 redwood city, ca 94063 tel: (650)568-5800 fax: (650)568-6165 email: info@haloelectronics.com website: http://www.haloelectronics.com transpower technologies, inc. corporate office park center west building 9805 double r blvd, suite # 100 reno, nv 89511 (800)500-5930 or (775)852-0140 email: info@trans-power.com website: http://www.trans-power.com
xrt73lc00a 32 rev. 1.0.2 e3/ds3/sts-1 line interface unit 3.0 the receive section figure 1 indicates that the xrt73lc00a receive section consists of the following blocks: ? agc/equalizer ? peak detector ? slicer ? clock recovery pll ? data recovery ? hdb3/b3zs decoder the purpose of the xrt73lc00a receive section is to take an incoming attenuat ed/distorted bipolar signal from the line and encode it back into the ttl/cmos fo rmat where it can be received and processed by digital circuitry in the terminal equipment. 3.1 interfacing the receive section of the xrt73lc00a to the line by design, the receive section of the xrt73lc00a can be transformer-coupled or capacitive-coupled to the line. the specification documents for e3, ds3 an d sts-1 all specify 75ohm termination loads when transmitting over coaxial cable. it is recommended to interface the receive section of the xrt73lc00a to the line as shown in figure 17 or figure 18 . f igure 17. r ecommended s chematic for i nterfacing the r eceive s ection of the xrt73lc00a to the l ine (t ransformer -c oupling ) bnc 1:1 r1 37.4 ? r2 37.4 ? rtip rring c1 0.01uf rpos rneg rclk1 rlos rlol rxlos rxlol rxpos rxneg rxlineclk t2
xrt73lc00a 33 e3/ds3/sts-1 line interface unit rev. 1.0.2 3.2 the receive equalizer block after the xrt73lc00a has received the incoming line sign al via the rtip and rring input pins, the first block that this signal passes through is the agc (automatic gain control) circuit followed by the receive equalizer. as the line signal is transmitted from a given transmit ting terminal, the pulse shapes at that location are basically square. these pulses consist of a combination of ?low? and ?high? frequency fourier components. as this line signal travels from the tr ansmitting terminal via the coaxial ca ble to the receiving terminal, it is subjected to frequency-dependent loss. the higher-frequency components of the signal is subjected to a greater amount of attenuation than the lower-frequency co mponents. if this line signal travels over reasonably long cable lengths (e.g., greater than 450 feet), then th e shape of the pulses which were originally square is distorted and inter-symbol interference increases. the purpose of the receive equalizer is to equalize the di stortion of the incoming signal due to cable loss. the receive equalizer accomplishes this by subjecting the received line signal to frequency-dependent amplification which attempts to coun ter the frequency dependent loss that the line signal has experienced and to restore the shape of the line signal so that the transmitted data and clock can be recovered reliably. 3.2.1 guidelines for setting the receive equalizer this data sheet presents guidelines for setting the receive equalizer, for the following conditions. 1. if the overall cable length from the local receiving te rminal to the remote transmitting terminal is not known. 2. if the overall cable length from the local receiving te rminal to the remote trans mitting terminal is known. 3.2.1.1 if the overall cable length is not known this section presents recommendations on what state to set the receive equalizer when the overall cable- length from the local receiving termina l to the remote transmitting termina l is not known. for ds3, sts-1 and e3 applications, enable the receive equalizer by sett ing either the reqdis inpu t pin ?low? or the reqdis bit-field to ?0?. the remainder of this section provides an explanation why we recommend enabling the receive equalizer for these applications. 3.2.1.1.1 the use of the receive eq ualizer in a typical ds3 or sts-1 application most system manufacturers of equipment supporting ds3 and sts-1 lines interface their equipment to either a dsx-3 or stsx-1 cross-connect. wh ile installing their equipment the trans mit line build-out circuit is set to the proper setting that makes the transmit output pulse compliant with the is olated dsx-3 or stsx-1 pulse f igure 18. r ecommended s chematic for i nterfacing the r eceive s ection of the xrt73lc00a to the l ine (c apacitive -c oupling ) r1 75 ? rtip rring c1 0.01uf c2 0.01uf receive line signal
xrt73lc00a 34 rev. 1.0.2 e3/ds3/sts-1 line interface unit template requirements. for the xrt73lc00a this is achieved by setting the txlev input pin or bit-field to the appropriate level. when the system manufacturer is interfacing the re ceive section of the xrt73lc00a to the cross-connect, they should keep aware of the following facts: 1. all ds3 or sts-1 line signals that are present at either the dsx-3 or the stsx-1 cross-connect are required to meet the isolated pulse template re quirements per bellcore gr-499-core for ds3 applica - tions or bellcore gr-253-core for sts-1 applications. 2. bellcore documents state that the amplitude of these pulses at the dsx-3 or stsx-1 can range in ampli - tude from 360mvpk to 850mvpk. 3. bellcore documents stipulate that the receiving terminal must be able to receive this pulse-template com - pliant line signal over a cable length of 0 to 450 feet from the dsx-3 or the stsx-1 cross connect. these facts are reflected in figure 19. design considerations for ds3 and sts-1 applications when installing equipment into envir onments as depicted in figure 18, th e system installati on personnel may be able to determine the cable length between the local terminal equipment and the dsx-3/stsx-1 cross- connect patch-panel. the cable length between the local terminal equipment and the dsx-3/stsx-1 cross- connect patch panel ranges between 0 and 450 feet. it is extremely unlikely that the sys tem installation personnel will know t he cable length between the dsx-3/ stsx-1 cross-connect patch-panel and the remote term inal equipment. we reco mmend that the receive equalizer be enabled by setting the reqdis input pin or bit-field to "0". f igure 19. t he t ypical a pplication for the s ystem i nstaller dsx-3 or stsx-1 digital cross- connect system transmitting terminal receiving terminal 0 to 450 feet of cable pulses that are compliant to the isolated dsx-3 or stsx-1 pulse template requirement 0 to 450 feet of cable
xrt73lc00a 35 e3/ds3/sts-1 line interface unit rev. 1.0.2 the only time the receive equalizer should be disabled is when there is an off-chip equalizer in the receive path between the dsx-3/stsx-1 cross-connect and the rt ip/rring input pins or, in applications where the receiver is monitoring the transmit output signal directly. 3.2.1.1.2 design considerations for e3 applications in e3 system installation, it is re commended that the receive equalizer of the xrt73lc00a be enabled by pulling the reqdis input pin to gnd or by setting the reqdis bit-field to ?0?. n ote : the results of extensive testing indicates that when the receive equalizer is enabled, the xrt73lc00a is capable of receiving an e3 line signal with anywhere from 0 to 12db of cable loss over the industrial temperature range. design considerations if the overall ca ble length is known if during system installation the overall cable length is kn own, then in order to optimize the performance of the xrt73lc00a in terms of rece ive intrinsic jitter, etc., the receive eq ualizer should be enabled or disabled based upon the following recommendations: the receive equalizer should be turned on if the rece ive section is going to receive a line signal with an overall cable length of 300 feet or greater. the receive equalizer should be turned off if the receive section is going to receive a line signal over a cable length of less than 300 feet. n otes : 1. if the receive equalizer block is turned on in a given receive section that is receiving a line signal over short cable length, there is the risk of over-equalizing the received line signal which could degrade performance by increasing the amount of jitter that exists in the reco vered data and clock signals or by creating bit-errors. 2. the receive equalizer has been designed to counter the frequency-dependent cable loss that a line signal experiences as it travels from the tr ansmitting terminal to the receiving terminal. however, receive equalizer was not designed to counter flat loss where all of the fourier frequency components in the line signal are subject to the same amount of attenuation. flat loss is handled by the agc block. the receive equalizer block can be disabled setting the reqdis input pin ?high? when operating in the hardware mode or wr iting a "1" to the reqdis bit-field in command register cr2 when operating the xrt73lc00a in the host mode. 3.3 peak detector and slicer after the incoming line signal has passed through the receiv e equalizer, it is routed to the slicer block. the purpose of the slicer is to quantify a given bit-period or symbol within the incoming line signal as either a ?1? or a ?0?. 3.4 clock recovery pll the output of the slicer, which is now dual-rail digita l pulses, is routed to the clock recovery pll. the purpose of the clock recovery pll is to track the incoming dual-rail data stream and to derive and generate a recovered clock signal. it is important to note that the cl ock recovery pll requires a line rate clock signal at the exclk input pin. the clock recovery pll operates in one of two modes: ? the training mode. ? the data/clock recovery mode 1. the training mode if the xrt73lc00a is not receiving a line signal via the rtip and rring input pins or if the frequency difference between the line signal and that appli ed via the exclk input pin exceeds 0.5%, then the command register cr2 (address = 0x02) d4 d3 d2 d1 d0 reserved endecdis alosdis dlosdis reqdis x x x x 1
xrt73lc00a 36 rev. 1.0.2 e3/ds3/sts-1 line interface unit xrt73lc00a liu ic is operating in the training mode. w hen the liu is operating in the training mode it does the following: a. declares a loss of lock indication by toggling the rlol output pin ?high? and b. outputs a clock signal via the rclk1 and rclk2 output pins which is derived from the signal applied to the exclk input pin. 2. the data/clock recovery mode if the frequency difference between the line signal and th at applied via the exclk input pin is less than 0.5%, the xrt73lc00a liu ic is operating in the data/clock recovery mode. in this mode, the clock recovery pll is locked onto the line signal via the rtip and rring input pins. 3.5 the hdb3/b3zs decoder the remote transmitting terminal typically encodes the line signal into some sort of zero suppression line code (e.g., hdb3 for e3 and b3zs for ds3 and sts-1). th e purpose of this encoding activity was to aid in the clock recovery process of this data in the near-end receiving terminal. once the data has made it across the e3, ds3 or sts-1 transport medium and has been recovered by the clock recovery pll, it is now necessary to restore the original content of the data. the purpose of the hdb3/b3zs decoding block is to restore the data transmitted over the e3, ds3 or sts-1 line to its original content prior to zero suppression encoding. 3.5.1 b3zs decoding ds 3/sts-1 applications if the xrt73lc00a is configured to operate in the ds 3 or sts-1 modes, then the hdb3/b3zs decoding block performs b3zs decoding. when the decoder is operati ng in this mode it parses through the incoming dual- rail data and checks for the occurrence of either a ?00v? or a ?b0v? pattern. if the b3zs decoder detects this particular pattern it substitutes these bits with a ?000? pattern. n ote : if the b3zs decoder detects any bipolar violations that is not in accordance with the?b3zs line code? format, or if the b3zs decoder detects a string of 3 (or more) consec utive ?0?s? in the incoming line signal, then the b3zs decoder flags this event as a line code violation by pulsing the lcv output pin ?high?. figure 20 illustrates the b3zs deco der at work with two separate zero s uppression patterns in the incoming dual-rail data stream. 3.5.2 hdb3 decoding e3 applications if the xrt73lc00a is configured to operate in the e3 mode, the hdb3/b3zs decoding block performs hdb3 decoding. when the decoder is operating in this mode it parses through the incoming dual-rail data and checks for the occurrence of either a ?000v? or a ?b00v? pattern. if the hdb3 decoder detects this particular pattern, it substitutes these bits with a ?0000? pattern. figure 21 illustrates the hdb3 decoder at work with two se parate zero suppr ession patterns in the incoming dual-rail data stream. f igure 20. a n e xample of b3zs d ecoding data 0 1 0 1 1 0 0 0 1 0 1 1 1 1 0 1 1 0 1 1 0 0 1 1 1 0 0 0 1 rpos rneg 0 0 v line signal b 0 v rclk
xrt73lc00a 37 e3/ds3/sts-1 line interface unit rev. 1.0.2 n ote : if the hdb3 decoder detects any bipolar violation (e.g., ?v?) pulses that is not in accordance with the hdb3 line code format, or if the hdb3 decoder detec ts a string of 4 (or more) ?0?s? in the incoming line signal, then the hdb3 decoder flags this event as a line code violation by pulsing the lcv output pin ?high?. 3.5.3 enabling/disabling the hdb3/b3zs decoder the hdb3/b3zs decoder of the xrt73lc00a can be en abled or disabled by either of the following means: if the xrt73lc00a is operat ing in the hardware mode: enable the hdb3/b3zs encode r/decoder by pulling th e endecdis input pin (pin 21) to gnd. to disable the hdb3/b3zs encoder/decoder, pull the endecdis input pin to vdd. if the xrt73lc00a is operating in the host mode: enable the xrt73lc00a hdb3/b3zs en coder/decoder by writing a ?0? in to the endecdis bit-field in command register cr2. to disa ble the hdb3/b3zs encoder/decoder, write a ?1? into the endecdis bit- field. 3.6 los declaration/clearance the xrt73lc00a contains circuitry that monitors the fo llowing two parameters associated with the incoming line signals. 1. the amplitude of the incoming line signal via the rtip and rring inputs; and 2. the number of pulses detected in the incoming line signal within a certain amount of time. if the xrt73lc00a determines that the incoming line signal is missing due to insufficient amplitude or a lack of pulses in the incoming line signal) then it declares a loss of signal (los) co ndition. the xrt73lc00a declares the los condition by toggling the rlos outpu t pin ?high? and by setting the rlos bit field in command register 0 to ?1?. if the xrt73lc00a determines that the incoming line signal has been restored (e.g., there is sufficient amplitude and pulses in the incoming line signal) then it clears the los condition by toggling the rlos output pin ?low? and setting the rlos bit-field to ?0?. the los declaration/clearance scheme that is em ployed in the xrt73lc00a is based upon itu-t recommendation g.775 for both e3 and ds3 applications. the los declaration and clearance criteria that the xrt73lc00a uses for each of these modes (e.g., e3 and ds3) are presented below. f igure 21. a n e xample of hdb3 d ecoding command register cr2 (address = 0x02) d4 d3 d2 d1 d0 reserved endecdis alosdis dlosdis reqdis x 0 x x x data 0 1 0 1 1 0 0 0 0 0 1 1 1 1 0 1 1 0 1 1 0 0 1 1 0 0 0 0 1 0 0 0 v line signal b 0 0 v rpos rneg rclk
xrt73lc00a 38 rev. 1.0.2 e3/ds3/sts-1 line interface unit 3.6.1 the los declaration/clearanc e criteria for e3 applications when the xrt73lc00a is operating in the e3 mode, it declares an los condition if the signal amplitude drops to -35db or below. the xrt73lc00a clears the lo s condition if the signal amplitude rises back up to - 15db or above. figure 22 illustrates the signal levels at whic h the xrt73lc00a asserts and clears los. timing requirements associated wi th declaring and clearing the lo s indicator for e3 applications the xrt73lc00a was designed to meet the itu-t g.775 specification timing requirements for declaring and clearing the los indicator. the xrt73lc00a declares an los between 10 and 255 ui or e3 bit-periods after the actual time the los condition oc curred. the xrt73lc00a clears the los indicator within 10 to 255 ui after restoration of the incoming line signal. figure 23 illustrates the los declar ation and clearance behavior in response to the first loss of signal event and then afterwards to the restoration of the signal. f igure 22. t he s ignal l evels that the xrt73lc00a d eclares and c lears los (e3 m ode o nly ) 0 db -12 db -15db -35db maximum cable loss for e3 los signal must be declared los signal must be cleared los signal may be cleared or declared
xrt73lc00a 39 e3/ds3/sts-1 line interface unit rev. 1.0.2 3.6.2 the los declaration/clearance cr iteria for ds3 and sts-1 applications when the xrt73lc00a is operating in the ds3 or sts-1 modes it declares and clears los based on either: ? analog los (alos) declarat ion/clearance criteria or, ? digital los (dlos) declar ation/clearan ce criteria in the ds3 or sts-1 modes the los ou tput (rlos) is simply the logical or of the alos and dlos states. 1. the analog los (alos) declaration/clearance criteria the xrt73lc00a declares an analog los (alos) condit ion if the amplitude of the incoming line signal drops below a specific amplitude as defined by the state of the losthr input pin. declaring alos the xrt73lc00a declares an alos (analog los) condit ion whenever the amplitude of the input signal falls below the signal level to declare alos levels specified in ta b l e 4 . clearing alos the xrt73lc00a clears alos whenever the amplitude of the input signal rises a bove the signal level to clear alos levels specified in ta b l e 4 . n ote : there is approximately a 2db hysteresis in the received signal level that exists between declaring and clearing alos in order to prevent chattering in the rlos output signal. monitoring the state of alos f igure 23. t he b ehavior of the los o utput i ndicator i n r esponse to the l oss of s ignal and the r es - toration of s ignal t able 4: t he alos (a nalog los) d eclare and c lear t hresholds for a given setting of losthr and reqen for ds3 and sts-1 a pplications a pplication reqen s etting losthr s etting s ignal l evel to d eclare alos s ignal l evel to c lear alos ds3 1 1 < 22mv > 90mv 0 1 < 17mv < 70mv sts-1 1 1 < 25mv > 115mv 0 1 < 20mv < 90mv actual occurrence of los condition line signal is restored time range for los declaration time range for los clearance g.775 compliance g.775 compliance 0 ui 10 ui 0 ui 10 ui 255 ui 255 ui rtip/ rring rlos output pin
xrt73lc00a 40 rev. 1.0.2 e3/ds3/sts-1 line interface unit if the xrt73lc00a is operating in the host mode, the state of alos can be polled or monitored by reading in the contents of command register 0. the bit- format of command register 0 is presented below. if the alos bit-field contains a ?1?, the xrt73lc00a is currently declaring an alos condition. if the alos bit- field contains a ?0?, the device is no t currently declaring an alos condition. disabling the alos detector it is useful to disable the alos detector in the xrt 73lc00a for debugging purposes. if the xrt73lc00a is operating in the host mode, the alos detector can be di sabled by writing a ?1? into the alosdis bit-field in command register 2 as depicted below. n ote : setting both the alosdis and dlosdis bit-fields to ?1? disables los declaration in the xrt73lc00a. 2. the digital los (dlos) declaration/clearance criteria the xrt73lc00a declare a digital los (dlos) cond ition if the xrt73lc00a detects 16032 or more consecutive ?0?s? in the incoming data. the xrt73lc00a clears dlos if it detects four consecut ive sets of 32 bit-periods each of which contains at least 10 ?1?s? (e.g., average pulse density of greater than 33%). monitoring the state of dlos if the xrt73lc00a is operating in the host mode, the state of dlos can be polled or monitored by reading in the contents of command register 0 as shown. if the dlos bit-field contains a ?1?, the xrt73lc00a is currently declaring a dlos condition. if the dlos bit- field contains a ?0?, the device is no t currently declaring the dlos condition. disabling the dlos detector command register cr0 (address = 0x00) d4 d3 d2 d1 d0 rlol rlos alos dlos dmo read only read only read only read only read only command register cr2 (address = 0x02) d4 d3 d2 d1 d0 reserved endecdis alosdis dlosdis reqdis x x 1 x x command register cr0 (address = 0x00) d4 d3 d2 d1 d0 rlol rlos alos dlos dmo read only read only read only read only read only
xrt73lc00a 41 e3/ds3/sts-1 line interface unit rev. 1.0.2 it is useful to disable the dlos detector in the xrt 73lc00a for debugging purposes. if the xrt73lc00a is operating in the host mode, the dlos detector can be disabled by writing a ?1? into the dlosdis bit-field in command register 2. n ote : setting both the alosdis and dlosdis bit-fields to a ?1? disables los declaration in the xrt73lc00a. 3.6.3 muting the recovered data while the los is being declared in some applications it is not desirable for the xrt73l c00a e3/ds3/sts-1 liu to recover data and route it to the receiving terminal while the liu is declaring a lo s condition. the los muting fe ature, if enabled, causes the xrt73lc00a to halt transmission of the recovered data to the receiving terminal while the los condition is true. in this case, the rpos and rneg output pins are forced to ?0?. once the los condition has been cleared, the xrt73lc00a resumes the transmission of the recovered data to the receiving terminal. the xrt73lc00a allows enabling of the muting upon los feature by either of the following means. if the xrt73lc00a is operat ing in the hardware mode: the muting upon los feature is enabled by pulling the losmuten input pin (pin 19) to vdd. if the xrt73lc00a is operating in the host mode: to enable this feature, access the microprocessor serial interface and write a ?1? into the losmut bit-field in command register 3. n ote : the xrt73lc00a automatically declares an los condition any time it has been configured to operate in either the analog local loop-back or digital local loop-back modes . muting -upon -los must be disabled prior to configuring the device to operate in either of these local loop-back modes. 3.7 routing the recovered timing and data information to the receiving terminal equipment the xrt73lc00a ultimately takes the recovered timing a nd data information, conver ts it into cmos levels and routes it to the receiving terminal equipment via the rpos, rneg, rclk1 and rclk2 output pins. the xrt73lc00a can deliver the recovered data and clock information to the receiving terminal in either a single-rail or dual-rail format. routing dual-rail format data to the receiving terminal equipment whenever the xrt73lc00a delivers dual-rail format to the terminal equipment it does so via the following output signals. n rpos n rneg n rclk1 n rclk2 figure 24 illustrates the typical in terface for the transmission of data in a dual-rail format from the receive section of the xrt73lc00a to the receiving terminal equipment. command register cr2 (address = 0x02) d4 d3 d2 d1 d0 reserved endecdis alosdis dlosdis reqdis x x x 1 x command register cr3 (address = 0x03) d4 d3 d2 d1 d0 rnrz losmut clk2dis rclk2inv clk1inv x 1 x x x
xrt73lc00a 42 rev. 1.0.2 e3/ds3/sts-1 line interface unit the manner that the liu transmits dual-rail data to th e receiving terminal equipment is described below and illustrated in figure 25 . the xrt73lc00a typically updates the data on the rpos and rneg output pins on the rising edge rclk1 (or rclk2). rclk1 (or rclk2) is the recovered clock signal from t he incoming received line signal. these clock signals are typically 34.368 mhz for e3 applications, 44.736 mhz for ds3 applications and 51.84 mhz for sonet sts-1 applications. if the xrt73lc00a received a positive-polarity pulse in the incoming line signal via the rtip and rring input pins, then the xrt73lc00a pulses the rpos output pin ?high?. if the xrt73lc00a received a negative- polarity pulse in the incoming line signal via the rtip and rring input pins, then the xrt73lc00a pulses the rneg output pin ?high?. inverting the rclk1 or rclk2 outputs when using the xrt73lc00a, either of the rclk1 or rclk2 signals can be inverted with respect to the delivery of the rpos and rneg output signals to the receiving terminal equipment. this feature may be useful for those customers whose receiving terminal equipment logic design is such that the rpos and rneg data must be sampled on the rising edge of rclk1 or rclk2. figure 26 illustrates the be havior of the rpos, rneg and rclk signals when the rclk signal has been inverted. f igure 24. t he t ypical i nterface for the t ransmission of d ata in a d ual -r ail f ormat f rom the r eceive s ection of the xrt73lc00a to the r eceiving t erminal e quipment f igure 25. h ow the xrt73lc00a o utputs d ata on the rpos and rneg o utput p ins exar e3/ds3/sts-1 liu receive logic block rxpos rxneg rclk1, 2 rpos rneg rclk1, 2 terminal equipment (e3/ds3 or sts-1 framer) rclk1 rpos rneg
xrt73lc00a 43 e3/ds3/sts-1 line interface unit rev. 1.0.2 to configure the xrt73lc00a to invert the rclk1 output signal, the xrt73lc00a must be operating in the host mode. this configuration can be implemented by accessing the microprocessor serial interface block and writing a ?1? into the rclk1inv bit-fiel d in command register cr3 to invert rclk1. the rclk2 output signal can also be inverted when th e xrt73lc00a is operating in the hardware mode by setting the rclk2inv input pin ?high?. 3.7.1 routing single-rail format data (binary da ta stream) to the receive terminal equipment to route single-rail format data (e.g., a binary data st ream) from the receive section of the xrt73lc00a to the receiving terminal eq uipment, do the following: a. configure the xrt73lc00a to operate in the host mode and b. access the microprocessor serial interface and write a ?1? into the rnrz bit-field in command register cr3. after these steps are taken, the xrt73lc00a outputs single-rail data to the receiving terminal equipment via the rpos and rclk1 (or rclk2) output pins as illustrated in figure 27 and figure 28 . n ote : the rneg output pin is internally tied to gnd whenever this feature is enabled. f igure 26. t he b ehavior of the rpos, rneg and rclk1 s ignals w hen rclk1 is i nverted command register cr3 (address = 0x03) d4 d3 d2 d1 d0 rnrz losmut clk2dis rclk2inv rclk1inv x x x 1 1 command register cr3 (address = 0x03) d4 d3 d2 d1 d0 rnrz losmut clk2dis rclk2inv rclk1inv 1 x x x x rclk1 rpos rneg
xrt73lc00a 44 rev. 1.0.2 e3/ds3/sts-1 line interface unit 4.0 diagnostic features of the xrt73lc00a the xrt73lc00a supports equipment diagnostic activi ties by supporting the following loop-back modes in the chip: ? analog local loop-back ? digital local loop-back ? remote loop-back. 4.1 the analog local loop-back mode when the xrt73lc00a is configured to operate in the analog local loop-back mode, the xrt73lc00a ignores any signals that are input to the rtip and rri ng input pins. the transmitting terminal equipment transmits clock and data into the xrt73lc00a via the tpdata, tndata and tclk input pins. this data is processed through the transmit clock duty cycle adjust pll and the hdb3/b3zs encoder. finally, this data outputs to the line via the ttip and tring output pins and is looped back into the agc/receive equalizer block. consequently, this data is also processed through the receive sect ion of the xrt73lc00a. after this post-loop-back data has been processed through the receive section it outputs to the near-end receiving terminal equipment via the rpos, rneg, rclk1 and rclk2 output pins. figure 29 illustrates the path that the data takes when the chip is configured to operate in the analog local loop-back mode. the xrt73lc00a can be configured to operate in the a nalog local loop-back mode by employing either one of the following two steps: f igure 27. t he t ypical i nterface for the t ransmission of d ata in a s ingle -r ail f ormat f rom the r eceive s ection of the xrt73lc00a to the r eceiving t erminal e quipment f igure 28. t he b ehavior of the rpos and rclk1 o utput s ignals w hile the xrt73lc00a is t ransmit - ting s ingle -r ail d ata to the r eceiving t erminal e quipment terminal equipment (e3/ds3 or sts-1 framer) exar e3/ds3/sts-1 liu receive logic block rxpos rclk1, 2 rpos rclk1, 2 rclk1 rpos
xrt73lc00a 45 e3/ds3/sts-1 line interface unit rev. 1.0.2 if the xrt73lc00a is operating in the host mode: access the microprocessor serial interface and write a ?1 ? into the llb bit-field and a ?0? into the rlb bit-field in command register 4. if the xrt73lc00a is operat ing in the hardware mode: the llb input pin (pin 14) must be set to ?high? and the rlb input pin (pin 15) must be set to ?low?. n otes : 1. the analog local loop-back mode does not work if the transmitter is turned off via the txoff feature. 2. the xrt73lc00a automatically declares an los condition anytime it has been configured to operate in either the analog local loop-back or digital local loop-back modes. consequently, the muting -upon -los must be disabled prior to configuring the device to operate in either of these local loop-back modes. 4.2 the digital local loop-back mode when the xrt73lc00a is configured to operate in th e digital local loop-back mode, it ignores any signals that are input to the rtip and rring input pins. th e transmitting terminal equipment transmits clock and data into the xrt73lc00a via the tpdata, tndata and tclk input pins. this data is processed through the transmit clock duty cycle adjust pll and the hdb3/b 3zs encoder block and then looped back to the hdb3/ b3zs decoder block. figure 30 illustrates the path that the data takes when the chip is conf igured to operate in the digital local loop-back mode. f igure 29. t he a nalog l ocal l oop -b ack in the xrt73lc00a command register cr4 (address = 0x04) d4 d3 d2 d1 d0 x sts-1/ ds3 e3 llb rlb x x x 1 0 agc/ equalizer peak detector los detector slicer clock recovery data recovery invert loop mux hdb3/ b3zs decoder losthr sdi sdo/lcv sclk cs regreset rtip rring reqdis rclk1 rclk2 rpos rneg dr/sr rlos llb rlb endecdis taos tpdata tndata tclk rlol exclk device monitor mtip mring transmit logic duty cycle adjust txlev txoff dmo ttip tring pulse shaping hdb3/ b3zs encoder serial processor interface analog local loop-back path
xrt73lc00a 46 rev. 1.0.2 e3/ds3/sts-1 line interface unit the digital local loop-back mode, along with the txoff feature, is useful in redundancy system design. these two features permit the system to execute some diagnostic tests in the back-up line card without transmitting data onto the line and interfering with the ds3/e3/sts-1 traffic from the primary line card. the xrt73lc00a can be configured to operate in the dig ital local loop-back mode by employing either one of the following two-steps. a. if the xrt73lc00a is operating in the host mode access the microprocessor serial interface and write a ?1? into both the llb and rlb bit-fields in command register 4. b. if the xrt73lc00a is operating in the hardware mode set both the llb input pin (pin 14) and the rlb input pin (pin 15) to ?high?. n otes : 1. the digital local loop-back mode feat ure works even if the transmitter is turned off via the txoff feature. 2. the xrt73lc00a automatically declares an los condition any time it has been configur ed to operate in either the analog local loop-back or digital local loop-back modes. consequently, the muting -upon -los must be disabled prior to configuring the device to operate in either of these local loop-back modes. 4.3 the remote loop-back mode when the xrt73lc00a is configured to operate in the remote loop-back mode, it ignores any signals that are input to the tpdata and tndata input pins. the xrt73lc00a receives the incoming line signal via the rtip and rring input pins. this data is processed through the receive section of the xrt73lc00a and outputs to the receive terminal equipment via the rpos, rneg, rclk1 and rclk2 output pins. additionally, this data is internally looped back into the pulse-shaping block in the transmit section. at this f igure 30. t he d igital l ocal l oop -b ack path in the xrt73lc00a command register cr4 (address = 0x04) d4 d3 d2 d1 d0 x sts-1/ ds3 e3 llb rlb x x x 1 1 agc/ equalizer peak detector los detector slicer clock recovery data recovery invert loop mux hdb3/ b3zs decoder losthr sdi sdo/lcv sclk cs regreset rtip rring reqdis rclk1 rclk2 rpos rneg dr/sr rlos llb rlb endecdis taos tpdata tndata tclk rlol exclk device monitor mtip mring transmit logic duty cycle adjust txlev txoff dmo ttip tring pulse shaping hdb3/ b3zs encoder serial processor interface digital local loop-back path
xrt73lc00a 47 e3/ds3/sts-1 line interface unit rev. 1.0.2 point, this data is routed through the remainder of the transmit section of the xrt73lc00a and transmitted out onto the line via the tt ip and tring output pins. figure 31 illustrates the path that the data takes in the xr t73lc00a when the chip is configured to operate in the remote loop-back mode. during remote loop-back operation, any data which is inputted via the rtip and rring input pins is also outputted to the terminal equipment via the rpos, rneg and rclk output pins. the xrt73lc00a can be configured to operate in the remote loop-back mode by employing either one of the following two steps if the xrt73lc00a is operating in the host mode: access the microprocessor serial interface and write a ?1? into the rlb bit-field and a ?0? in the llb bit-field in command register cr4. if the xrt73lc00a is operat ing in the hardware mode: set the rlb input pin (pin 15) to ?high? and the llb input pin (pin 16) to ?low?. 4.4 txoff features the xrt73lc00a allows the transmit dr iver in the transmit section of the chip to be shut off. this feature can be advantageous for system redundancy conditions or during diagnostic testing. this feature can be activated by either of the following ways. when the xrt73lc00a is opera ting in the hardware mode f igure 31. t he r emote l oop -b ack p ath in the xrt73lc00a command register cr4 (address = 0x04) d4 d3 d2 d1 d0 x sts-1/ ds3 e3 llb rlb x x x 0 1 agc/ equalizer peak detector los detector slicer clock recovery data recovery invert loop mux hdb3/ b3zs decoder losthr sdi sdo/lcv sclk cs regreset rtip rring reqdis rclk1 rclk2/lcv rpos rneg dr/sr rlos llb rlb endecdis taos tpdata tndata tclk rlol exclk device monitor mtip mring transmit logic duty cycle adjust txlev txoff dmo ttip tring pulse shaping hdb3/ b3zs encoder serial processor interface remote loop-back path
xrt73lc00a 48 rev. 1.0.2 e3/ds3/sts-1 line interface unit shut off the transmit driver by toggling the txoff input pin (pin 35) ?high?. turn on the transmit driver by toggling the txoff input pin ?low?. when the xrt73lc00a is operating in the host mode if the xrt73lc00a is operating in the host mode, the txoff input pin is disabled. consequently, thetransmit driver is turned off by writing to command regist er cr1 and setting the txoff bit-field (bit d4) to ?1?. n ote : if the transmitter is shut off via the txoff feature, t he xrt73lc00a can not be conf igured to operate in the analog local loop-back mode. to perform diagnostics on the chip and still invoke the txoff feature as in system redundancy applications, use the digital local loop-back feature instead. 4.5 the transmit drive monitor features the transmit drive monitor feature performs monitoring of the line in the transmit direction for the occurrence of fault conditions such as a short circuit on the line or a defective transmit drive in the xrt73lc00a. the transmit drive monitor is activated by connecting the mtip pin (pin 44) to the ttip line through a 270 ? resistor connected in series and by connecting the mring pin (pin 43) to the tring line through a 270 ? resistor connected in se ries, as illustrated in figure 32 . when the transmit drive monitor circuitry is connected to the line as illustrated in figu re 26, then it monitors the line for transitions. as long as the transmit drive monitor circuitry detects transitions on the line via the mtip and mring pins, it keeps the dmo (drive monitor ou tput) signal ?low?. however, if the transmit drive monitor circuit detects no transitions on the line for 12 832 tclk periods, then the dmo signal toggles ?high?. n otes : 1. the transmit drive monitor circuit does not have to be used to operate the transmit section of the xrt73lc00a. this is purely a diagnostic feature. 2. the transmit drive monitor feature can also be used to moni tor the transmit output line signal of another liu ic as illustrated in figure 33 . command register cr1 (address = 0x01) d4 d3 d2 d1 d0 txoff taos txclkinv txlev txbin 1 x x x x f igure 32. t he xrt73lc00a e mploying the t ransmit d rive m onitor f eatures r1 = 31.6 ? r2 = 31.6 ? ttip tring 1:1 mtip mring r3 = 270 ? r4 = 270 ? t1 r5 = 75 ?
xrt73lc00a 49 e3/ds3/sts-1 line interface unit rev. 1.0.2 presented in figure 33, if liu # 1 (u1) fails, then liu # 2 (u2) drives its dmo output pin ?high?. likewise, if liu # 2 (u2) fails, then liu # 1 (u1) drives its dmo output pin ?high?. the scheme presented in figure 33 is a better design approach. it overcomes situations in which a liu monitoring its own signal ( figure 32 ) may experience a failure mode such that it cannot drive a bipolar signal onto the line. that same failure mode may prevent the liu from dr iving the dmo output pin ?high?. 4.6 the taos (transmit all ones) feature the xrt73lc00a can transmit an all ?1?s? pattern onto the line by toggling a single input pin or by setting a single bit-field in one of the command registers to ?1?. n ote : when this feature is activa ted, the transmit section of the xrt73lc 00a overwrites the terminal equipment data with this all ?1?s? pattern. this feature can be activated by either of the following methods. f igure 33. t wo liu? s , e ach m onitoring the t ransmit o utput s ignal of the o ther liu ic r1 31.6 ? bnc t1 r2 31.6 ? r7 31.6 ? bnc r8 31.6 ? ttip tring r3 270 ? r4 270 ? r5 270 ? r6 270 ? tring ttip mring mtip mring mtip dmo_channel_2 dmo_channel_1 dmo dmo t2 pe-68629 pe-68629 txoff txoff u1 u2
xrt73lc00a 50 rev. 1.0.2 e3/ds3/sts-1 line interface unit when the xrt73lc00a is opera ting in the hardware mode: configure the device to transmit an all ?1?s? pattern by to ggling the taos input pin (pin 2) ?high?. terminate the all ?1?s? pattern by toggling the taos input pin ?low?. when the xrt73lc00a is operating in the host mode: if the xrt73lc00a is operating in the host mode, th e taos input pin is disabled. consequently, the xrt73lc00a can be configured to transmit an all ?1?s? pattern by writing to command register cr1 and setting the taos bit-field (bit d3) to ?1?. the all ?1?s? pattern can be terminat ed by writing to command register cr1 and setting the taos bit-field (d3) to ?0". command register cr1 (address = 0x01) d4 d3 d2 d1 d0 txoff taos txclkinv txlev txbin 0 1 x x x
xrt73lc00a 51 e3/ds3/sts-1 line interface unit rev. 1.0.2 5.0 the microprocessor serial interface the on-chip command registers of th e xrt73lc00a ds3/e3/sts-1 line interface unit ic are accessed to configure the xrt73lc00a into a variety of modes. this section describes the command registers and how to use the microprocessor serial interface. 5.1 description of the command registers a listing of these command regist ers, their addresses and their bit-formats are listed in table 5. address: the register addresses are in hexadecimal format. type: the command registers are either read-only (ro) or read/write (r/w) registers. n otes : 1. the default value for each of the bit-fields in these registers is ?0?. 2. if the regreset input pin is asserted, then the c ontents of the command registers is reset to all "0's" resulting in the xrt73lc00a operating in the mode corresponding to the default values of the command registers. description of bit-fields for each command register 5.1.1 command register - cr0 bit d4 - rlol (receive loss of lock status) this read-only bit-field reflects the lock status of the clock recovery phase-locked-loop in the xrt73lc00a. t able 5: a ddresses and b it f ormats of xrt73lc00a c ommand r egisters a ddress c ommand r egister t ype r egister b it -f ormat d4 d3 d2 d1 d0 0x00 cr0 ro rlol rlos alos dlos dmo 0x01 cr1 r/w txoff taos txclkinv txlev txbin 0x02 cr2 r/w reserved endecdis alosdis dlosdis reqdis 0x03 cr3 r/w rnrz losmut rclk2/ lcv rclk2inv rclk1inv 0x04 cr4 r/w reserved sts-1/ ds3 e3 llb rlb 0x05 cr5 r/w reserved reserved reserved reserved reserved 0x06 cr6 r/w reserved reserved reserved reserved reserved 0x07 cr7 r/w reserved reserved reserved reserved reserved 0x08 cr8 r/w reserved reserved reserved reserved reserved 0x09 cr9 r/w reserved reserved reserved reserved reserved 0x10 cr10 r/w reserved reserved reserved reserved reserved 0x11 cr11 r/w reserved reserved reserved reserved reserved 0x12 cr12 r/w reserved reserved reserved reserved reserved 0x13 cr13 r/w reserved reserved reserved reserved reserved 0x14 cr14 r/w reserved reserved reserved reserved reserved 0x15 cr15 r/w reserved reserved reserved reserved reserved
xrt73lc00a 52 rev. 1.0.2 e3/ds3/sts-1 line interface unit this bit-field is set to ?0? if the clock recovery pll is in lock with the incomi ng line signal. this bit-field is set to ?1? if the clock recovery pll is out of lock with the incoming line signal. bit d3 - rlos (receive loss of signal status) this read-only bit-field indicates whether or not the re ceiver in the xrt73lc00a is currently declaring an los (loss of signal) condition. this bit-field is set to ?0? if the xrt7 3lc00a is not currently declaring the los condition. this bit-field is set to ?1? if the xrt73lc00a is declaring an los condition. bit d2 - alos (analog loss of signal status) this read-only bit-field indicates whether or not the analog los detector in th e xrt73lc00a is currently declaring an los condition. this bit-field is set to ?0? if the analog los detector in the xrt73lc00a is not currently declaring an los condition. conversely , this bit-field is set to ?1? if the analog los detector is currently declaring an los condition. the purpose of this feature is to isolate either the anal og los or the digital los detector that is declaring the los condition. this feature may be usef ul for troubleshooting/debugging purposes. bit d1 - dlos (digital loss of signal status) this read-only bit-field indicates whether or not the digital los detector in the xrt73lc00a is currently declaring an los condition. this bit-field is set to ?0? if the digital los detector in the xrt73lc00a is not currently declaring an los condition. conversely, this bit-fiel d is set to ?1? if the digital los de tector is currently declaring an los condition. n ote : the purpose of this feature is to isolate the detector (e.g., either the analog los or the digital los detector) that is declaring the los condition. this feature may be useful for troubleshooting/debugging purposes. bit d0 - dmo (drive monitor output status) this read-only bit-field reflects the status of the dmo output pin. 5.1.2 command register - cr1 bit d4 - txoff (transmitter off) this read/write bit-field is used to tu rn off the transmitter in the xrt73lc00a. writing a ?1? to this bit-field turns off the transmitter and tr i-states the transmit output. writing a ?0? to this bit- field turns on the transmitter. bit d3 - taos (transmit all ones) this read/write bit-field is used to command the xrt73lc00a transmitter to generate and transmit an all ?1?s? pattern onto the line. writing a ?1? to this bit-field commands the transmitter to transmit an all ?1?s? pattern onto the line. writing a ?0? to this bit-field commands normal operation. bit d2 - txclkinv (transmit clock invert) this read/write bit-field is used to configure the xrt73l c00a transmitter to sample the signal at the tpdata and tndata pins on the rising or falling edg e of tclk (the transmit line clock signal). writing a ?1? to this bit-field configures the transmitte r to sample the tpdata and tndata input pins on the rising edge of tclk. writing a ?0? to this bit-field configures the transmitter to sample the tpdata and tndata input pins on the falling edge of tclk. bit d1 - txlev (transmit level select) this read/write bit-field is used to enable or di sable the xrt73lc00a transmit line build-out circuit. setting this bit-field "high" disables the line build-o ut circuit of the xrt73lc00a. in this mode, the xrt73lc00a outputs partially-shaped pulses onto the li ne via the ttip and tring output pins. setting this bit-field "low" enables the line build-out circuit of the xrt73lc00a. in this mode the xrt73lc00a outputs shaped pulses onto the line via the ttip and tring output pins.
xrt73lc00a 53 e3/ds3/sts-1 line interface unit rev. 1.0.2 to comply with the isolated dsx/stsx-1 pulse templa te requirements per bellcore gr-499-core or gr- 253-core, either: 1. set this input pin to "1" if the ca ble length between the cross-connect and the transmit output of the xrt73lc00a is greater than 225 feet or 2. set this input pin to "0" if the ca ble length between the cross-connect and the transmit output of the xrt73lc00a is less than 225 feet. n ote : this option is only available when the xrt73lc00a is operating in the ds3 or sts-1 mode. bit d0 - txbin (transmit binary data) this read/write bit-field permits configuring of the tr ansmitter in the xrt73lc00a to accept an un-encoded binary data stream via the tpdata input and converts this data into the appropriate bipolar signal to the line. writing a ?1? configures the transmitter to acce pt a binary data stream via the tpdata input. n ote : the tndata input is ignored. this form of data acceptance is sometimes referred to as single-rail mode operation. the transmitter then encodes this data into the appropriate line code (e.g., b3zs or hdb3) prior to its transmission over the line. writing a ?0? configures the transmitter to accept data in a dual-rail manner (e.g., via both the tpdata and tndata inputs).
xrt73lc00a 54 rev. 1.0.2 e3/ds3/sts-1 line interface unit 5.1.3 command register - cr2 bit d4 - reserved this bit-field has no defined functionality bit d3 - endecdis (b3zs/hdb 3 encoder/decoder-disable) this read/write bit-field is used to enable or di sable the b3zs/hdb3 encoder/decoder in the xrt73lc00a. writing a ?1? to this bit-field disables the b3zs/hdb3 enco der. writing a ?0? to this bit-field enables the b3zs/ hdb3 encoder. n ote : this encoder performs hdb3 encoding if the xrt73lc00a is operating in the e3 mode. otherwise, it performs b3zs encoding. bit d2 - alosdis (analog los disable) this read/write bit-field is used to disable the analog los detector. writing a ?0? to this bit-field enables the analog los detect or. writing a ?1? to this bit-field disables the analog los detector. n ote : if the analog los detector is disabled, then the rlos input pin is only asserted by the dlos (digital los detector). bit d1 - dlosdis (digital los disable) this read/write bit-field is used to disable the digital los detector. writing a ?0? to this bit-field enables the digital los detect or. writing a ?1? to this bit-field disables the digital los detector. n ote : if the digital los detector is disabled, then the rlos input pin is only asserted by the alos (analog los detector). bit d0 - reqdis (receive equalization disable) this read/write bit-field is used to either enable or disable the internal receive equalizer in the xrt73lc00a. writing a ?0? to this bit-field enables the internal equalizer . writing a ?1? to this bit-field disables the internal equalizer. 5.1.4 command register - cr3 bit d4 - rnrz (receive binary data) this read/write bit-field is used to configure the xrt73lc00a to output the received data from the remote terminal in a binary or dual-rail format. writing a ?1? to this bit-field configures the xrt73lc00a to output data to the terminal equipment in a single- rail (binary) format via the rpos output pin. the rneg is grounded. a ?0? to this bit-field configures the xrt73lc00a to output data to the terminal equipmen t in a dual-rail format via both the rpos and rneg output pins. bit d3 - losmut (recovered data muting during los condition) this read/write bit-field is used to configure the xrt7 3lc00a to not output any re covered data while it is declaring an los condition to the terminal equipment. writing a ?0? to this bit-field configures the chip to output recovered data even while the xrt73lc00a is declaring an los condition. writing a ?1? to this bit-fi eld configures the chip to not output the recovered data while an los condition is being declared. n ote : in this mode, rpos and rneg is set to ?0? asynchronously. bit d2 - rclk2/ lcv (receive clock output 2/line code violation) this read/write bit-field is used to select the function of pin 30 (rclk2/lcv). pin 30 can be configured to function as the line code violation output indicator or as the additional rece ive clock output (rclk2). writing a ?0? to this bit-field configures the pin to function as the line code violation output pin. writing a ?1? to this bit-field configures this pin to function as the rclk2 output pin. bit d1 - rclk2inv (invert rclk2)
xrt73lc00a 55 e3/ds3/sts-1 line interface unit rev. 1.0.2 this read/write bit-field is used to configure the receiver in the xrt73lc00a to output the recovered data on either the rising edge or the fa lling edge of the rclk2 clock signal. writing a ?0? to this bit-field configures the receiver to output the recovered data on the rising edge of the rclk2 output signal. writing a ?1? to this bit-field conf igures the receiver to output the recovered data on the falling edge of the rc lk2 output signal. bit d0 - rclk1inv (invert rclk1) this read/write bit-field is used to configure the receiver in the xrt73lc00a to output the recovered data on either the rising edge or the fa lling edge of the rclk1 clock signal. writing a ?0? to this bit-field configures the receiver to output the recovered data on the rising edge of the rclk1 output signal. writing a ?1? to this bit-field conf igures the receiver to output the recovered data on the falling edge of the rc lk1 output signal. 5.1.5 command register - cr4 bit d4 - reserved this bit-field has no defined functionality bit d3 - sts-1/ds3 mode select this read/write bit-field is used to configure the xrt7 3lc00a to operate in either the sonet sts-1 mode or the ds3 mode. writing a ?0? into this bit-field configures the xrt73lc00a to operate in the ds3 mode. writing a ?1? into this bit-field configures the xrt73lc00a to operate in the sonet sts-1 mode. n ote : this bit-field is ignored if the e3 bit-field (d2 in this command register) is set to ?1?. bit d2 - e3 mode select this read/write bit-field is used to configure the xrt73lc00a to operate in the e3 mode. writing a ?0? into this bit-field configures the xrt73lc00a to operate in either the ds3 or sonet sts-1 mode specified by the setting of the ds3 bit- field in this command register. writing a ?1? into this bit-field configures the xrt73lc00a to operate in the e3 mode. bit d1 - llb (local loop-back) this read/write bit-field along with rl b (bit d0 in this comma nd register) is used to select which loop-back mode the xrt73lc00a operates in. ta b l e 6 relates the state of the llb and rlb to the selected loop-back mode. bit d0 - rlb (remote loop-back) this read/write bit-field along with llb (bit d1 in th is command register) is used to select which loop-back mode the xrt73lc00a operate in. ta b l e 6 relates the state of the llb and rlb bits to the selected loop- back mode. 5.2 operating the microprocessor serial interface. the xrt73lc00a serial interface is a simple four wir e interface that is compat ible with many of the microcontrollers available in the market. this interface consists of the following signals: t able 6: l oop -b ack m odes llb (b it d1) rlb (b it d0) l oop -b ack m ode 0 0 no loop-back mode (normal operation) 0 1 remote loop-back mode 1 0 analog loop-back mode 1 1 digital loop-back mode
xrt73lc00a 56 rev. 1.0.2 e3/ds3/sts-1 line interface unit cs - chip select (active low) sclk - serial clock sdi - serial data input sdo - serial data output using the microprocessor serial interface the following instructions for using the microprocessor se rial interface are best understood by referring to the diagram in figure 34 . in order to use the microprocessor serial interface, a clock signal must be supplied to the sclk input pin. a read or write operation can then be initiated by asserting the active-low chip select input pin ( cs ). it is important to assert the cs pin (e.g., toggle it ?low?) at least 5ns prior to the very first rising edge of the clock signal. once the cs input pin has been asserted, the type of operatio n and the target register address must now be specified. this inform ation is supplied to the microprocessor serial in terface by writing eight serial bits of data into the sdi input. n ote : each of these bits is clocked into the sdi input on the rising edge of sclk. these eight bits are identified and described below. bit 1 - r/w (read/write) bit this bit is clocked into the sdi input on the first rising edge of sclk after cs has been asserted. this bit indicates whether the current operation is a read or wr ite operation. a ?1? in this bit specifies a read operation, a ?0? in this bi t specifies a write operation. bits 2 through 5: the four (4) bit address values (labeled a0, a1, a2 and a3) the next four rising edges of the sclk signal clock in th e 4-bit address value for this particular read (or write) operation. the address selects the command register in the xrt73lc00a that the user is either reading data from or writing data to. the address bits must be supplied to the sdi input pin in ascending order with the lsb (least significant bit) first. bits 6 and 7: the next two bits, a4 and a5 must be set to ?0? as shown in figure 34. bit 8: the value of a6 is a ?don?t care?. f igure 34. m icroprocessor s erial i nterface d ata s tructure d0 d1 d2 d7 d6 d5 d4 d3 high z sdo a0 d0 r/w d1 a6 0 0 a3 a2 a1 d7 d6 d5 d4 d3 d2 sdi 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 sclk cs high z - denotes a ?don?t care? value a4 and a5 are always ?0?. r/w = ?1? for ?read? operations r/w = ?0? for ?write? operations notes: - denotes a ?don?t care? value a4 and a5 are always ?0?. r/w = ?1? for ?read? operations r/w = ?0? for ?write? operations notes:
xrt73lc00a 58 rev. 1.0.2 e3/ds3/sts-1 line interface unit ordering information package dimensions p roduct n umber p ackage o perating t emperature r ange xrt73lc00aiv 44 pin tqfp (10mm x 10mm -40 0 c to +85 0 c 33 23 22 12 111 34 44 d d 1 d d 1 b e ? a 2 a 1 a seating plane l c 44 lead thin quad flat pack (10 x 10 x 1.4 mm tqfp) rev. 1.00 note: the control dimension is the millimeter column symbol min max min max a 0.055 0.063 1.4 1.6 a1 0.002 0.006 0.05 0.15 a2 0.053 0.057 1.35 1.45 b 0.012 0.018 0.3 0.45 c 0.004 0.008 0.09 0.2 d 0.465 0.48 11.8 12.2 d1 0.39 0.398 9.9 10.1 e l 0.018 0.03 0.45 0.75 ? 0 o 7 o 0 o 7 o inches millimeters 0.0315 bsc 0.80 bsc
xrt73lc00a 59 notice exar corporation reserves the right to make changes to the products contained in this publicat ion in order to improve design, performanc e or reliability. exar corp oration assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infr ingement. charts and schedules contai ned here in are only for illustration purposes and may vary depending upon a user?s specific application. while the information in this publication has been carefully ch ecked; no responsibility, however , is assumed for inaccuracies. exar corporation does not re commend the use of any of its products in life suppo rt applications where the failure or malfunction of the product can reasonably be ex pected to cause failure of the life support system or to significantly affect its safety or effectiveness. products ar e not authorized for use in such applications unless exar corporation receives , in writing, assuranc es to its satisfaction that: (a) th e risk of injury or damage has been minimized; (b) th e user assumes all such ris ks; (c) potential liability of exar corporation is adequately protected under the circumstances. copyright 2011 exar corporation datasheet may 2011. reproduction, in part or whole, without the prior written consent of exar co rporation is prohibited. e3/ds3/sts-1 line interface unit rev. 1.0.2 revision history r evision # d ate d escription 1.0.0 november 2004 original xrt73lc00a document. 1.0.1 august 2008 updated datasheet headers. corrected figure 10 block diagram typo. rede - fined t 22 serial processor interface timing. 1.0.2 may 2011 changed the description for the ttip and tring pins in the pin defini - tion table to accurately reflect their functions.

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